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beltino: Fix up device tree

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- eDP / DisplayPort / Panel settings
- Add PCI subsystem ID
- Fix SuperIO range decode

BUG=none
TEST=Boot ChromeOS on Beltino
BRANCH=none

Change-Id: I95a868c981f7f348a907bff7a9980ba83e9ffdb4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172932
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
This commit is contained in:
Stefan Reinauer 2013-10-11 16:10:46 -07:00 • committed by chrome-internal-fetch
commit a1a55a9530
1 changed files with 7 additions and 19 deletions
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26
src/mainboard/google/beltino/devicetree.cb
View file

@ -1,26 +1,14 @@
chip northbridge/intel/haswell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Disable eDP Hotplug
register "gpu_dp_d_hotplug" = "0x00"
# Disable DisplayPort C Hotplug
register "gpu_dp_c_hotplug" = "0x00"
# Enable DisplayPort C Hotplug with 6ms pulse
register "gpu_dp_c_hotplug" = "0x06"
# Enable HDMI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4)
register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2)
register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7)
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5)
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6)
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
@ -40,6 +28,7 @@ chip northbridge/intel/haswell
end
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
@ -54,9 +43,8 @@ chip northbridge/intel/haswell
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
# SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701"
# EC_SMI is GPIO34
register "alt_gp_smi_en" = "0x0004"