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soc/intel/skl: Replace dt HeciEnabled by HECI1 disable config

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List of changes:

1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.

Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2022-01-03 18:07:13 +00:00
commit a0d9ad322f
37 changed files with 48 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/soc/intel/skylake/chip.c
View file

@ -410,11 +410,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PowerLimit4 = 0;
/*
* To disable HECI, the Psf needs to be left unlocked
* by FSP till end of post sequence. Based on the devicetree
* by FSP till end of post sequence. Based on the config
* setting, we set the appropriate PsfUnlock policy in FSP,
* do the changes and then lock it back in coreboot during finalize.
*/
tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
tconfig->PchSbAccessUnlock = CONFIG(DISABLE_HECI1_AT_PRE_BOOT);
const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
tconfig->PchLockDownBiosInterface = lockdown_by_fsp;

5
src/soc/intel/skylake/chip.h
View file

@ -395,11 +395,6 @@ struct soc_intel_skylake_config {
* 3 = GT unsliced, 4 = GT sliced
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
/*
* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS
*/
u8 HeciEnabled;
/*
* Enable VR specific mailbox command

8
src/soc/intel/skylake/finalize.c
View file

@ -44,15 +44,11 @@ static void pch_disable_heci(void)
static void pch_finalize_script(struct device *dev)
{
config_t *config;
tco_lockdown();
/* Display me status before we hide it */
intel_me_status();
config = config_of(dev);
/*
* Set low maximum temp value used for dynamic thermal sensor
* shutdown consideration.
@ -62,8 +58,8 @@ static void pch_finalize_script(struct device *dev)
*/
pch_thermal_configuration();
/* we should disable Heci1 based on the devicetree policy */
if (config->HeciEnabled == 0)
/* we should disable Heci1 based on the config */
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
pch_disable_heci();
/* Hide p2sb device as the OS must not change BAR0. */