diff --git a/romimages/RON_VIA_SPD/Makefile b/romimages/RON_VIA_SPD/Makefile index 6b766b35a4..e1a54a5630 100644 --- a/romimages/RON_VIA_SPD/Makefile +++ b/romimages/RON_VIA_SPD/Makefile @@ -8,7 +8,7 @@ CPUFLAGS += -DNEWPCI CPUFLAGS += -DSERIAL_CONSOLE # mainboard-dependent. CPUFLAGS += -DPM_DEVFN=0x3c -CPUFLAGS += -DSUPERIO_DEVFN=0x88 +CPUFLAGS += -DSUPERIO_DEVFN=0x38 # If you enable FIXED_AND_VARIABLE it never makes it to the kernel! # you have to only enable variable. # 1/25/01. Things just stopped working for no reason I can see (RGM). diff --git a/romimages/RON_VIA_SPD/crt0.S b/romimages/RON_VIA_SPD/crt0.S index 372ba2bcfc..e7ee6bfd8b 100644 --- a/romimages/RON_VIA_SPD/crt0.S +++ b/romimages/RON_VIA_SPD/crt0.S @@ -29,7 +29,7 @@ #include /* turn on serial */ -#include +#include #include #include diff --git a/romimages/RON_VT5259A/Makefile b/romimages/RON_VT5259A/Makefile index fadaa36850..64efcf9648 100644 --- a/romimages/RON_VT5259A/Makefile +++ b/romimages/RON_VT5259A/Makefile @@ -11,7 +11,7 @@ CPUFLAGS += -DSERIAL_CONSOLE #CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS # mainboard-dependent. CPUFLAGS += -DPM_DEVFN=0x3c -CPUFLAGS += -DSUPERIO_DEVFN=0x88 +CPUFLAGS += -DSUPERIO_DEVFN=0x38 CPUFLAGS += -DRAMTEST # This makes it fail sooner ... #CPUFLAGS += -DINBUF_COPY diff --git a/romimages/RON_VT5259A/crt0.S b/romimages/RON_VT5259A/crt0.S index c385449478..e7ee6bfd8b 100644 --- a/romimages/RON_VT5259A/crt0.S +++ b/romimages/RON_VT5259A/crt0.S @@ -1,3 +1,6 @@ +/* + v1.0 02/15/2001: To add "afteram.inc" file after test dram. +*/ /* * $ $ * @@ -26,17 +29,22 @@ #include /* turn on serial */ -#include +#include #include +#include +/* + */ TTYS0_TX_STRING($ttyS0_test) /* initialize the RAM */ /* different for each motherboard */ -#include - +#include +#include +#include + #ifdef RAMTEST #include @@ -47,6 +55,8 @@ CALLSP(ramtest) #endif + +#include /* * Copy data into RAM and clear the BSS. Since these segments * isn't really that big we just copy/clear using bytes, not diff --git a/romimages/RON_VT5426/crt0.S b/romimages/RON_VT5426/crt0.S index 6017aac98b..71fd810073 100644 --- a/romimages/RON_VT5426/crt0.S +++ b/romimages/RON_VT5426/crt0.S @@ -26,7 +26,7 @@ #include /* turn on serial */ -#include +#include #include #include diff --git a/src/southbridge/via/vt8231/southbridge.c b/src/southbridge/via/vt8231/southbridge.c index dc35153f6d..4150017c6d 100644 --- a/src/southbridge/via/vt8231/southbridge.c +++ b/src/southbridge/via/vt8231/southbridge.c @@ -6,24 +6,24 @@ void keyboard_on() { volatile unsigned char regval; - /* regval = intel_conf_readb(0x8000385A); */ + /* regval = intel_conf_readb(0x80008851); */ /*regval |= 0x01; */ - regval = 0xff; - intel_conf_writeb(0x8000385A, regval); + regval = 0xcf; + intel_conf_writeb(0x80008851, regval); /* disable USB1 */ - intel_conf_writeb(0x80003A3C, 0x00); - intel_conf_writeb(0x80003A04, 0x00); - regval = intel_conf_readb(0x80003848); - regval |= 0x04; - intel_conf_writeb(0x80003848, regval); + intel_conf_writeb(0x80008A3C, 0x00); + intel_conf_writeb(0x80008A04, 0x00); + regval = intel_conf_readb(0x80008850); + regval |= 0x10; + intel_conf_writeb(0x80008850, regval); /* disable USB2 */ - intel_conf_writeb(0x80003B3C, 0x00); - intel_conf_writeb(0x80003B04, 0x00); - regval = intel_conf_readb(0x80003885); - regval |= 0x10; - intel_conf_writeb(0x80003885, regval); + intel_conf_writeb(0x80008B3C, 0x00); + intel_conf_writeb(0x80008B04, 0x00); + regval = intel_conf_readb(0x80008850); + regval |= 0x20; + intel_conf_writeb(0x80008850, regval); pc_keyboard_init(); @@ -34,7 +34,7 @@ void nvram_on() /* the VIA 686A South has a very different nvram setup than the piix4e ... */ /* turn on ProMedia nvram. */ /* TO DO: use the PciWriteByte function here. */ - intel_conf_writeb(0x80003843, 0xFF); + intel_conf_writeb(0x80008841, 0xFF); } void southbridge_fixup() @@ -45,45 +45,45 @@ void southbridge_fixup() // enable the internal I/O decode // to do: use the pcibios_find function here, instead of // hard coding the devfn. - devfn = PCI_DEVFN(7, 0); - enables = pcibios_read_config_byte(0, devfn, 0x81, &enables); + devfn = PCI_DEVFN(17, 0); + enables = pcibios_read_config_byte(0, devfn, 0x6C, &enables); enables |= 0x80; - pcibios_write_config_byte(0, devfn, 0x81, enables); + pcibios_write_config_byte(0, devfn, 0x6C, enables); #ifndef DISABLE_SOUTHBRIDGE_COM_PORTS // enable com1 and com2. - enables = pcibios_read_config_byte(0, devfn, 0x83, &enables); + enables = pcibios_read_config_byte(0, devfn, 0x6e, &enables); // 0x80 is enable com port b, 0x1 is to make it com2, 0x8 is enable com port a as com1 enables = 0x80 | 0x1 | 0x8 ; - pcibios_write_config_byte(0, devfn, 0x83, enables); + pcibios_write_config_byte(0, devfn, 0x6e, enables); // note: this is also a redo of some port of assembly, but we want everything up. // set com1 to 115 kbaud // not clear how to do this yet. // forget it; done in assembly. #endif // enable IDE, since Linux won't do it. - // First do some more things to devfn (7,0) + // First do some more things to devfn (17,0) // note: this should already be cleared, according to the book. - pcibios_read_config_byte(0, devfn, 0x48, &enables); - printk("IDE enable in reg. 48 is 0x%x\n", enables); - enables &= ~2; // need manifest constant here! - printk("set IDE reg. 48 to 0x%x\n", enables); - pcibios_write_config_byte(0, devfn, 0x48, enables); + pcibios_read_config_byte(0, devfn, 0x50, &enables); + printk("IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk("set IDE reg. 50 to 0x%x\n", enables); + pcibios_write_config_byte(0, devfn, 0x50, enables); // set default interrupt values (IDE) - pcibios_read_config_byte(0, devfn, 0x4a, &enables); - printk("IRQs in reg. 4a are 0x%x\n", enables & 0xf); + pcibios_read_config_byte(0, devfn, 0x4c, &enables); + printk("IRQs in reg. 4c are 0x%x\n", enables & 0xf); // clear out whatever was there. enables &= ~0xf; enables |= 4; - printk("setting reg. 4a to 0x%x\n", enables); - pcibios_write_config_byte(0, devfn, 0x4a, enables); + printk("setting reg. 4c to 0x%x\n", enables); + pcibios_write_config_byte(0, devfn, 0x4c, enables); // set up the serial port interrupts. // com2 to 3, com1 to 4 - pcibios_write_config_byte(0, devfn, 0x52, 0x34); - - devfn = PCI_DEVFN(7, 1); + pcibios_write_config_byte(0, devfn, 0x46, 0x04); + pcibios_write_config_byte(0, devfn, 0x47, 0x03); + devfn = PCI_DEVFN(17, 1); pcibios_read_config_byte(0, devfn, 0x40, &enables); printk("enables in reg 0x40 0x%x\n", enables); enables |= 3; diff --git a/src/superio/via/vt8231/setup_serial.inc b/src/superio/via/vt8231/setup_serial.inc new file mode 100644 index 0000000000..74b577b98d --- /dev/null +++ b/src/superio/via/vt8231/setup_serial.inc @@ -0,0 +1,55 @@ +/* + * Enable the serial evices on the VIA + */ + + +/* The base address is 0x15c, 0x2e, depending on config bytes */ + +#define SIO_BASE $0x3f0 +#define SIO_DATA SIO_BASE+1 + +#define WRITESUPER(register, value) movb register, %al ;\ + movw SIO_BASE, %dx ;\ + outb %al, %dx ;\ + movb value, %al ;\ + movw SIO_DATA, %dx ;\ + outb %al, %dx +#define WRITESIOBYTE(register, value) movw register, %dx ;\ + movb value, %al ;\ + outb %al, %dx +#define WRITESIOWORD(register, value) movw register, %dx ;\ + movw value, %ax ;\ + outw %ax, %dx +/* registers we use: 85, and the southbridge devfn is defined by the mainboard + */ +#define SUPERIOCONFIG CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50) +/* first, you have to enable the superio and superio config. + put a 3 in devfn 38 register 85 + */ + movl $SUPERIOCONFIG, %eax + movb $6, %dl + PCI_WRITE_CONFIG_BYTE +// now go ahead and set up com1. +// set address + WRITESUPER($0xf4, $0xfe) +// enable serial out + WRITESUPER($0xf2, $7) +// That's it for the sio stuff. +// movl $SUPERIOCONFIG, %eax +// movb $9, %dl +// PCI_WRITE_CONFIG_BYTE +// set up register to set baud rate. + WRITESIOBYTE($0x3fb, $0x80) +// Set 115 kb + WRITESIOWORD($0x3f8, $1) +// Set 9.6 kb +// WRITESIOWORD($0x3f8, $12) +// now set no parity, one stop, 8 bits + WRITESIOBYTE($0x3fb, $3) +// now turn on RTS, DRT + WRITESIOBYTE($0x3fc, $3) +// Enable interrupts + WRITESIOBYTE($0x3f9, $0xf) +// should be done. Dump a char for fun. + WRITESIOBYTE($0x3f8, $48) + diff --git a/src/superio/via/vt8231/superio.c b/src/superio/via/vt8231/superio.c new file mode 100644 index 0000000000..c93ee58ec1 --- /dev/null +++ b/src/superio/via/vt8231/superio.c @@ -0,0 +1,19 @@ +void +final_superio_fixup() +{ + unsigned int devfn = SUPERIO_DEVFN; + unsigned char enables; + + /* enable com ports, since we're using this built-in superio */ + // enable com1 and com2. + enables = pcibios_read_config_byte(0, devfn, 0x6e, &enables); + // 0x80 is enable com port b, 0x1 is to make it com2, 0x8 is enable com port a as com1 + enables = 0x80 | 0x1 | 0x8 ; + pcibios_write_config_byte(0, devfn, 0x6e, enables); + // note: this is also a redo of some port of assembly, but we want everything up. + // set com1 to 115 kbaud + // not clear how to do this yet. + // forget it; done in assembly. + +} + diff --git a/src/superio/via/vt82c686/setup_serial.inc b/src/superio/via/vt82c686/setup_serial.inc index e0e9afac93..34656f32c0 100644 --- a/src/superio/via/vt82c686/setup_serial.inc +++ b/src/superio/via/vt82c686/setup_serial.inc @@ -20,10 +20,13 @@ #define WRITESIOWORD(register, value) movw register, %dx ;\ movw value, %ax ;\ outw %ax, %dx +/* registers we use: 85, and the southbridge devfn is defined by the mainboard + */ +#define SUPERIOCONFIG CONFIG_ADDR(0, SUPERIO_DEVFN, 0x85) /* first, you have to enable the superio and superio config. put a 3 in devfn 38 register 85 */ - movl $0x3885, %eax + movl $SUPERIOCONFIG, %eax movb $3, %dl PCI_WRITE_CONFIG_BYTE // now go ahead and set up com1. @@ -32,7 +35,7 @@ // enable serial out WRITESUPER($0xe2, $7) // That's it for the sio stuff. - movl $0x3885, %eax + movl $SUPERIOCONFIG, %eax movb $9, %dl PCI_WRITE_CONFIG_BYTE // set up register to set baud rate.