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UPSTREAM: Ignore RAMTOP for MTRRs

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Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.

With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.

Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355006
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-19 20:38:41 +03:00 • committed by chrome-bot
commit 9f6c5b9b5b
18 changed files with 35 additions and 33 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/cpu/intel/car/cache_as_ram_ht.inc
View file

@ -388,7 +388,7 @@ no_msr_11e:
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
rdmsr
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
#if CACHE_ROM_SIZE

4
src/cpu/intel/haswell/romstage.c
View file

@ -119,9 +119,9 @@ static void *setup_romstage_stack_after_car(void)
slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
num_mtrrs++;

2
src/cpu/intel/model_2065x/cache_as_ram.inc
View file

@ -233,7 +233,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr

2
src/cpu/intel/model_206ax/cache_as_ram.inc
View file

@ -243,7 +243,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr

2
src/cpu/intel/model_6ex/cache_as_ram.inc
View file

@ -182,7 +182,7 @@ clear_mtrrs:
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr