Massive resync of my tree and freebios-cvs including.

- Motherboard identification in the linuxbios table.
- Better SMP startup code.
- Support for the tyan s2462, the supermicro p4dc6, the supermicro p4dc6+, and the beginnings of supermicro p4dpr support
- Remove of no longer needed USE_AMD_NDA option

src/include/boot/linuxbios_table.h

@@ -18,6 +18,7 @@ struct lb_record *lb_new_record(struct lb_header *header);
 struct lb_memory *lb_memory(struct lb_header *header);
 void lb_memory_range(struct lb_memory *mem, 
 	uint32_t type, unsigned long start, unsigned long size);
+struct lb_mainboard *lb_mainboard(struct lb_header *header);
 unsigned long lb_table_fini(struct lb_header *header);
 
 /* Routines to extract part so the linuxBIOS table or information

src/include/boot/linuxbios_tables.h

@@ -79,6 +79,15 @@ struct lb_hwrpb {
 	uint64_t hwrpb;
 };
 
+#define LB_TAG_MAINBOARD	0x0003
+struct lb_mainboard {
+	uint32_t tag;
+	uint32_t size;
+	uint8_t  vendor_idx;
+	uint8_t  part_number_idx;
+	uint8_t  strings[0];
+};
+
 
 
 /* The following structures are for the cmos definitions table */

src/include/cpu/i786/thermal_monitoring.h

@@ -0,0 +1,3 @@
+#define THERMAL_MONITORING_OFF 0
+#define THERMAL_MONITORING_SET 0x00000008
+#define MISC_ENABLE 0x01a0

src/include/cpu/k7/mtrr.h

@@ -3,10 +3,26 @@
 
 #include <cpu/p6/mtrr.h>
 
-#define TOP_MEM    0xc001001A
-#define TOP_MEM2   0xc001001D
 #define IORR_FIRST 0xC0010016
 #define IORR_LAST  0xC0010019
 #define SYSCFG     0xC0010010
 
+#define MTRR_READ_MEM			(1 << 4)
+#define MTRR_WRITE_MEM			(1 << 3)
+
+#define SYSCFG_MSR			0xC0010010
+#define SYSCFG_MSR_MtrrFixDramEn	(1 << 18)
+#define SYSCFG_MSR_MtrrFixDramModEn	(1 << 19)
+#define SYSCFG_MSR_MtrrVarDramEn	(1 << 20)
+
+
+#define IORR0_BASE			0xC0010016
+#define IORR0_MASK			0xC0010017
+#define IORR1_BASE			0xC0010018
+#define IORR1_MASK			0xC0010019
+#define TOP_MEM				0xC001001A
+#define TOP_MEM2			0xC001001D
+#define HWCR_MSR			0xC0010015
+
+
 #endif /* CPU_K7_MTRR_H */

src/include/pc80/mc146818rtc.h

@@ -88,6 +88,10 @@
 #define PC_CKS_RANGE_END	45
 #define PC_CKS_LOC		46
 
+#define LB_CKS_RANGE_START	49
+#define LB_CKS_RANGE_END	125
+#define LB_CKS_LOC		126
+
 #if !defined(ASSEMBLY)
 void rtc_init(int invalid);
 #if USE_OPTION_TABLE == 1

src/include/pci_ids.h

@@ -1226,6 +1226,17 @@
 #define PCI_DEVICE_ID_INTEL_82801BA_1F4	0x2444
 #define PCI_DEVICE_ID_INTEL_82801BA_1F5	0x2445
 
+#define PCI_DEVICE_ID_INTEL_82801CA_1E0	0x244e
+#define PCI_DEVICE_ID_INTEL_82801CA_1F0	0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_1F1 0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_1D2 0x2482
+#define PCI_DEVICE_ID_INTEL_82801CA_1F3 0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_1D1 0x2484
+#define PCI_DEVICE_ID_INTEL_82801CA_1F5 0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_1D2 0x2487
+
+#define PCI_DEVICE_ID_INTEL_82870_1F0	0x1461
+
 #define PCI_DEVICE_ID_INTEL_82820FW_0	0x2440
 #define PCI_DEVICE_ID_INTEL_82820FW_1	0x2442
 #define PCI_DEVICE_ID_INTEL_82820FW_2	0x2443

src/include/southbridge/amd/amd766.h

@@ -0,0 +1,19 @@
+#ifndef AMD766_H
+#define AMD766_H
+
+void amd766_disable_watchdog(void);
+void amd766_enable_ioapic(void);
+void amd766_enable_port92_reset(void);
+void amd766_mouse_sends_irq12(void);
+void amd766_enable_serial_irqs(int continuous, unsigned frames, unsigned startclocks);
+void amd766_cpu_reset_sends_init(void);
+#define DECODE_STPGNT_ADDR 0
+#define DECODE_STPGNT_DATA 1 
+void amd766_decode_stop_grant(unsigned how);
+void amd766_set_pm_classcode(void);
+void amd766_usb_setup(void);
+void amd766_power_after_power_fail(int on);
+void amd766_posted_memory_write_enable(void);
+void amd766_hard_reset(void);
+void amd766_enable_ide(int enable_a, int enable_b);
+#endif /* AMD766_H */