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This patch does some minor fixups for 8111 and 8132 and adds support for 8131.

Browse source 
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1098 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2009-01-05 23:02:16 +00:00
commit 9e1275fd39
8 changed files with 476 additions and 15 deletions
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3
Kconfig
View file

@ -132,6 +132,9 @@ config SOUTHBRIDGE_AMD_AMD8151
config SOUTHBRIDGE_AMD_AMD8132
select PCIX_SUPPORT
boolean
config SOUTHBRIDGE_AMD_AMD8131
select PCIX_SUPPORT
boolean
config SOUTHBRIDGE_AMD_AMD8111
boolean
config SOUTHBRIDGE_AMD_SB600

6
southbridge/amd/amd8111/stage1_smbus.c
View file

@ -22,15 +22,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#include <types.h>
#include <lib.h>
#include <console.h>
#include <device/pci.h>
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
#include <statictree.h>
#include <config.h>
#include "amd8111.h"
#include "amd8111_smbus.h"
#define SMBUS_IO_BASE 0x0f00

26
southbridge/amd/amd8131/Makefile Normal file
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@ -0,0 +1,26 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8131),y)
STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/amd8131/amd8131_bridge.c
endif

399
southbridge/amd/amd8131/amd8131_bridge.c Normal file
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@ -0,0 +1,399 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2003-2004 Linux Networx
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <lib.h>
#include <console.h>
#include <device/pci.h>
#include <mc146818rtc.h>
#include <device/pcix.h>
#include <device/pci_ids.h>
#define NMI_OFF 0
static void amd8131_walk_children(struct bus *bus,
void (*visit)(struct device * dev, void *ptr), void *ptr)
{
struct device * child;
for(child = bus->children; child; child = child->sibling)
{
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
amd8131_walk_children(&child->link[0], visit, ptr);
}
visit(child, ptr);
}
}
struct amd8131_bus_info {
unsigned sstatus;
unsigned rev;
int errata_56;
int master_devices;
int max_func;
};
static void amd8131_count_dev(struct device * dev, void *ptr)
{
struct amd8131_bus_info *info = ptr;
/* Don't count pci bridges */
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
info->master_devices++;
}
if (PCI_FUNC(dev->path.pci.devfn) > info->max_func) {
info->max_func = PCI_FUNC(dev->path.pci.devfn);
}
}
static void amd8131_pcix_tune_dev(struct device * dev, void *ptr)
{
struct amd8131_bus_info *info = ptr;
unsigned cap;
unsigned status, cmd, orig_cmd;
unsigned max_read, max_tran;
int sib_funcs, sibs;
struct device * sib;
if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
return;
}
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!cap) {
return;
}
/* How many siblings does this device have? */
sibs = info->master_devices - 1;
/* Count how many sibling functions this device has */
sib_funcs = 0;
for(sib = dev->bus->children; sib; sib = sib->sibling) {
if (sib == dev) {
continue;
}
if (PCI_SLOT(sib->path.pci.devfn) != PCI_SLOT(dev->path.pci.devfn)) {
continue;
}
sib_funcs++;
}
printk(BIOS_DEBUG,"%s AMD8131 PCI-X tuning\n", dev_path(dev));
status = pci_read_config32(dev, cap + PCI_X_STATUS);
orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
/* Errata #49 don't allow 4K transactions */
if (max_read >= 2) {
max_read = 2;
}
/* Errata #37 Limit the number of split transactions to avoid starvation */
if (sibs >= 2) {
/* At most 2 outstanding split transactions when we have
* 3 or more bus master devices on the bus.
*/
if (max_tran > 1) {
max_tran = 1;
}
}
else if (sibs == 1) {
/* At most 4 outstanding split transactions when we have
* 2 bus master devices on the bus.
*/
if (max_tran > 3) {
max_tran = 3;
}
}
else {
/* At most 8 outstanding split transactions when we have
* only one bus master device on the bus.
*/
if (max_tran > 4) {
max_tran = 4;
}
}
/* Errata #56 additional limits when the bus runs at 133Mhz */
if (info->errata_56 &&
(PCI_X_SSTATUS_MFREQ(info->sstatus) == PCI_X_SSTATUS_MODE1_133MHZ))
{
unsigned limit_read;
/* Look at the number of siblings and compute the
* largest legal read size.
*/
if (sib_funcs == 0) {
/* 2k reads */
limit_read = 2;
}
else if (sib_funcs <= 1) {
/* 1k reads */
limit_read = 1;
}
else {
/* 512 byte reads */
limit_read = 0;
}
if (max_read > limit_read) {
max_read = limit_read;
}
/* Look at the read size and the nubmer of siblings
* and compute how many outstanding transactions I can have.
*/
if (max_read == 2) {
/* 2K reads */
if (max_tran > 0) {
/* Only 1 outstanding transaction allowed */
max_tran = 0;
}
}
else if (max_read == 1) {
/* 1K reads */
if (max_tran > (1 - sib_funcs)) {
/* At most 2 outstanding transactions */
max_tran = 1 - sib_funcs;
}
}
else {
/* 512 byte reads */
max_read = 0;
if (max_tran > (2 - sib_funcs)) {
/* At most 3 outstanding transactions */
max_tran = 2 - sib_funcs;
}
}
}
#if 0
printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n",
dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs);
#endif
if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
cmd &= ~PCI_X_CMD_MAX_READ;
cmd |= max_read << 2;
}
if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
cmd &= ~PCI_X_CMD_MAX_SPLIT;
cmd |= max_tran << 4;
}
/* Don't attempt to handle PCI-X errors */
cmd &= ~PCI_X_CMD_DPERR_E;
/* The 8131 does not work properly with relax ordering enabled.
* Errata #58
*/
cmd &= ~PCI_X_CMD_ERO;
if (orig_cmd != cmd) {
pci_write_config16(dev, cap + PCI_X_CMD, cmd);
}
}
static unsigned int amd8131_scan_bus(struct bus *bus,
unsigned min_devfn, unsigned max_devfn, unsigned int max)
{
struct amd8131_bus_info info;
struct bus *pbus;
unsigned pos;
/* Find the children on the bus */
max = pci_scan_bus(bus, min_devfn, max_devfn, max);
/* Find the revision of the 8131 */
info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION);
/* See which errata apply */
info.errata_56 = info.rev <= 0x12;
/* Find the pcix capability and get the secondary bus status */
pos = pci_find_capability(bus->dev, PCI_CAP_ID_PCIX);
info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
/* Print the PCI-X bus speed */
printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus));
/* Examine the bus and find out how loaded it is */
info.max_func = 0;
info.master_devices = 0;
amd8131_walk_children(bus, amd8131_count_dev, &info);
/* Disable the bus if there are no devices on it or
* we are running at 133Mhz and have a 4 function device.
* see errata #56
*/
if (!bus->children ||
(info.errata_56 &&
(info.max_func >= 3) &&
(PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_MODE1_133MHZ)))
{
unsigned pcix_misc;
/* Disable all of my children */
disable_children(bus);
/* Remember the device is disabled */
bus->dev->enabled = 0;
/* Disable the PCI-X clocks */
pcix_misc = pci_read_config32(bus->dev, 0x40);
pcix_misc &= ~(0x1f << 16);
pci_write_config32(bus->dev, 0x40, pcix_misc);
return max;
}
/* If we are in conventional PCI mode nothing more is necessary.
*/
if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
return max;
}
/* Tune the devices on the bus */
amd8131_walk_children(bus, amd8131_pcix_tune_dev, &info);
/* Don't allow the 8131 or any of it's parent busses to
* implement relaxed ordering. Errata #58
*/
for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
bus_path(pbus));
pbus->disable_relaxed_ordering = 1;
}
return max;
}
static unsigned int amd8131_scan_bridge(struct device * dev, unsigned int max)
{
return do_pci_scan_bridge(dev, max, amd8131_scan_bus);
}
static void amd8131_pcix_init(struct device * dev)
{
u32 dword;
u16 word;
u8 byte;
int nmi_option;
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
byte |= 0x10;
pci_write_config8(dev, 0x04, byte);
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
word = 0x0404;
pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
word = 0x0404;
pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
word = 0x0404;
pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
/* Errata #51 */
word = pci_read_config16(dev, 0x4c);
word |= 1;
pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
pci_write_config16(dev, 0xaa, word);
word = pci_read_config16(dev, 0xac);
pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
}
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
pci_write_config32(dev, 0xc4, dword);
dword = pci_read_config32(dev, 0xc8);
dword |= (1<<1);
pci_write_config32(dev, 0xc8, dword);
}
return;
}
struct device_operations amd8131_pcix = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8131_PCIX}}},
.constructor = default_device_constructor,
.reset_bus = pci_bus_reset,
.phase3_scan = amd8131_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = amd8131_pcix_init,
.ops_pci = &pci_bus_ops_pci,
};
static void ioapic_enable(struct device * dev)
{
u32 value;
value = pci_read_config32(dev, 0x44);
if (dev->enabled) {
value |= ((1 << 1) | (1 << 0));
} else {
value &= ~((1 << 1) | (1 << 0));
}
pci_write_config32(dev, 0x44, value);
}
static struct pci_operations pci_ops_pci_dev = {
.set_subsystem = pci_dev_set_subsystem,
};
struct device_operations amd8131_apic = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8131_IOAPIC}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase3_chip_setup_dev = ioapic_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_ops_pci_dev,
};

23
southbridge/amd/amd8131/apic.dts Normal file
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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
device_operations = "amd8131_apic";
};

23
southbridge/amd/amd8131/pcix.dts Normal file
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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
{
device_operations = "amd8131_pcix";
};

1
southbridge/amd/amd8132/Makefile
View file

@ -23,5 +23,4 @@ ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8132),y)
STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/amd8132/amd8132_bridge.c
endif

10
southbridge/amd/amd8132/amd8132_bridge.c
View file

@ -23,13 +23,7 @@
#include <console.h>
#include <device/pci.h>
#include <device/pcix.h>
#include <msr.h>
#include <legacy.h>
#include <device/pci_ids.h>
#include <statictree.h>
#include <config.h>
#define NMI_OFF 0
/* We don't implement this because:
* 1. There's only one pair of registers for both devices.
@ -324,12 +318,11 @@ struct device_operations amd8132_pcix = {
.phase3_scan = amd8132_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = amd8132_pcix_init,
.ops_pci = &pci_bus_ops_pci,
};
static void ioapic_enable(struct device * dev)
{
u32 value;
@ -342,6 +335,7 @@ static void ioapic_enable(struct device * dev)
}
pci_write_config32(dev, 0x44, value);
}
static void amd8132_ioapic_init(struct device * dev)
{
u32 dword;