diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index eba870feba..346d88d575 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -138,6 +138,9 @@ config BOARD_GOOGLE_LAPIS select HAVE_SLP_S0_GATE select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD +config BOARD_GOOGLE_MOONSTONE + select BOARD_GOOGLE_MODEL_KINMEN + if BOARD_GOOGLE_FATCAT_COMMON config BASEBOARD_DIR @@ -176,6 +179,7 @@ config DRIVER_TPM_I2C_BUS default 0x01 if BOARD_GOOGLE_MODEL_FELINO default 0x03 if BOARD_GOOGLE_MODEL_KINMEN default 0x03 if BOARD_GOOGLE_LAPIS + default 0x03 if BOARD_GOOGLE_MOONSTONE config HAVE_SLP_S0_GATE def_bool n @@ -193,6 +197,7 @@ config MAINBOARD_PART_NUMBER default "Felino" if BOARD_GOOGLE_MODEL_FELINO default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN default "Lapis" if BOARD_GOOGLE_LAPIS + default "Moonstone" if BOARD_GOOGLE_MOONSTONE config MEMORY_SOLDERDOWN def_bool n @@ -206,6 +211,7 @@ config TPM_TIS_ACPI_INTERRUPT default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11) default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02) default 66 if BOARD_GOOGLE_LAPIS # GPE0_DW2_02 (GPP_E02) + default 66 if BOARD_GOOGLE_MOONSTONE # GPE0_DW2_02 (GPP_E02) # FIXME: update as per board schematics config UART_FOR_CONSOLE @@ -222,6 +228,7 @@ config VARIANT_DIR default "felino" if BOARD_GOOGLE_MODEL_FELINO default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN default "lapis" if BOARD_GOOGLE_LAPIS + default "moonstone" if BOARD_GOOGLE_MOONSTONE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name index 06e24e70f6..46b7158971 100644 --- a/src/mainboard/google/fatcat/Kconfig.name +++ b/src/mainboard/google/fatcat/Kconfig.name @@ -40,3 +40,6 @@ config BOARD_GOOGLE_KINMEN config BOARD_GOOGLE_LAPIS bool "-> Lapis" + +config BOARD_GOOGLE_MOONSTONE + bool "-> Moonstone" diff --git a/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk new file mode 100644 index 0000000000..cbe8155bd4 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/fatcat/variants/moonstone/gpio.c b/src/mainboard/google/fatcat/variants/moonstone/gpio.c new file mode 100644 index 0000000000..9a28421783 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/gpio.c @@ -0,0 +1,456 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* GPP_A00: ESPI_IO0_EC_R */ + /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ + + /* GPP_A01: ESPI_IO1_EC_R */ + /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */ + + /* GPP_A02: ESPI_IO2_EC_R */ + /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */ + + /* GPP_A03: ESPI_IO3_EC_R */ + /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */ + + /* GPP_A04: ESPI_CS0_EC_R_N */ + /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */ + + /* GPP_A05: ESPI_CLK_EC_R */ + /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */ + + /* GPP_A06: ESPI_RST_EC_R_N */ + /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ + + /* GPP_A08: NC */ + PAD_NC(GPP_A08, NONE), + /* GPP_A09: NC */ + PAD_NC(GPP_A09, NONE), + /* GPP_A10: NC */ + PAD_NC(GPP_A10, NONE), + /* GPP_A11: NC */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12: NC */ + PAD_NC(GPP_A12, NONE), + /* GPP_A13: MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_A13, NONE, DEEP), + /* GPP_A15: NC */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A16, 1, DEEP), + /* GPP_A17: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + + /* GPP_B00: USBC_SML_CLK_PD */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), + /* GPP_B01: USBC_SML_DATA_PD */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), + /* GPP_B02: NC */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03: NC */ + PAD_NC(GPP_B03, NONE), + /* GPP_B04: NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05: ISH_GP_1_SNSR_HDR */ + PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), + /* GPP_B06: NC */ + PAD_NC(GPP_B06, NONE), + /* GPP_B07: NC */ + PAD_NC(GPP_B07, NONE), + /* GPP_B08: NC */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09: NC */ + PAD_NC(GPP_B09, NONE), + /* GPP_B10: NC */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11: USB_OC1 */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* GPP_B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: DISP_HPD4 */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + /* GPP_B15: NC */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16: GEN5_SSD_PWREN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + /* GPP_B17: NC */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: NC */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21: TCP_RETIMER_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* GPP_B22: ISH_GP_5_SNSR_HDR */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), + /* GPP_B23: NC */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24: MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_B24, NONE, DEEP), + /* GPP_B25: MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_B25, NONE, DEEP), + + /* GPP_C00: NC */ + PAD_NC(GPP_C00, NONE), + /* GPP_C01: NC */ + PAD_NC(GPP_C01, NONE), + /* GPP_C02: NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03: NC */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04: NC */ + PAD_NC(GPP_C04, NONE), + /* GPP_C05: NC */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06: EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_C06, 1, DEEP), + /* GPP_C07: MEM_CH_SEL */ + PAD_CFG_GPI(GPP_C07, NONE, DEEP), + /* GPP_C08: NC */ + PAD_NC(GPP_C08, NONE), + /* GPP_C09: NC */ + PAD_NC(GPP_C09, NONE), + /* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + /* GPP_C11: NC */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12: NC */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13: CLKREQ4_X1_GEN4_M2_WLAN_N */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: NC */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), + /* GPP_C16: TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: NC */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19: NC */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20: TBT_LSX2_TXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21: TBT_LSX2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22: DDP3_CTRLCLK */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: DDP3_CTRLDATA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + + /* GPP_D00: NC */ + PAD_NC(GPP_D00, NONE), + /* GPP_D01: NC */ + PAD_NC(GPP_D01, NONE), + /* GPP_D02: SOC_WP_OD */ + PAD_CFG_GPI(GPP_D02, NONE, DEEP), + /* GPP_D03: NC */ + PAD_NC(GPP_D03, NONE), + /* GPP_D04: NC */ + PAD_NC(GPP_D04, NONE), + /* GPP_D05: disable ISH_UART0_RXD */ + PAD_NC(GPP_D05, NONE), + /* GPP_D07: NC */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08: NC */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09: I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10: HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11: HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + /* GPP_D12: HDA_SDO */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* GPP_D13: HDA_SDI0 */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D14: NC */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15: NC */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16: DMIC_CLK */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), + /* GPP_D17: DMIC_DATA */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), + /* GPP_D18: NC */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19: NC */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20: CSE_EARLY_SW */ + PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL), + /* GPP_D21: NC */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22: NC */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23: NC */ + PAD_NC(GPP_D23, NONE), + /* GPP_D24: MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_D24, NONE, DEEP), + /* GPP_D25: NC */ + PAD_NC(GPP_D25, NONE), + + /* GPP_E01: NC */ + PAD_NC(GPP_E01, NONE), + /* GPP_E02: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E03: GEN5_SSD_RESET_N */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E05: TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_E05, 0, PLTRST), + /* GPP_E06: NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E08: NC */ + PAD_NC(GPP_E08, NONE), + /* GPP_E09: USB_OC0 */ + PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), + /* GPP_E10: NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11: GPSI0_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5), + /* GPP_E12: TCHPAD_I2C4_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), + /* GPP_E13: TCHPAD_I2C4_SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), + /* GPP_E14: NC */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: NC */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: GSPI0_CS0 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), + /* GPP_E18: TCHPAD_INT# */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E19: FPMCU_PWREN */ + PAD_CFG_GPO(GPP_E19, 1, DEEP), + /* GPP_E20: FPMCU_FW_UPDATE */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E22: FPS_SOC_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT), + + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06: NC */ + PAD_NC(GPP_F06, NONE), + /* GPP_F07: NC */ + PAD_NC(GPP_F07, NONE), + /* GPP_F08: EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), + /* GPP_F09: NC */ + PAD_NC(GPP_F09, NONE), + /* GPP_F10: ISH_GP_6_SNSR_HDR */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8), + /* GPP_F11: NC */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12: TCHSCR_I2C5_SCL */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), + /* GPP_F13: TCHSCR_I2C5_SDA */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), + /* GPP_F14: GPSI0A_MOSI */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), + /* GPP_F15: GSPI0A_MISO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), + /* GPP_F16: TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* GPP_F17: NC */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18: TCHSCR_INT_L */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE), + /* GPP_F19: NC */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20: NC */ + PAD_NC(GPP_F20, NONE), + /* GPP_F22: NC */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: NC */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00: NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01: NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02: NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H03: NC */ + PAD_NC(GPP_H03, NONE), + /* GPP_H04: NC */ + PAD_NC(GPP_H04, NONE), + /* GPP_H05: NC */ + PAD_NC(GPP_H05, NONE), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: UART0_BUF_RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART0_BUF_TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10: NC */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11: NC */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13: CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14: NC */ + PAD_NC(GPP_H14, NONE), + /* GPP_H15: NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H16: NC */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17: NC */ + PAD_NC(GPP_H17, NONE), + /* GPP_H19: NC */ + PAD_NC(GPP_H19, NONE), + /* GPP_H20: NC */ + PAD_NC(GPP_H20, NONE), + /* GPP_H21: NC */ + PAD_NC(GPP_H21, NONE), + /* GPP_H22: NC */ + PAD_NC(GPP_H22, NONE), + + /* GPP_S00: SNDW3_CLK_CODEC */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SNDW3_DATA0_CODEC */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SNDW3_DATA1_CODEC */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* GPP_S03: SNDW3_DATA2_CODEC */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* GPP_S04: DMIC_CLK_A0 */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* GPP_S05: DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* GPP_S06: NC */ + PAD_NC(GPP_S06, NONE), + /* GPP_S07: NC */ + PAD_NC(GPP_S07, NONE), + + /* GPP_V00: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01: BC_ACOK_MCP */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02: LANWAKE_N_R */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: PWRBTN_MCP_N */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04: PM_SLP_S3_N */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05: PM_SLP_S4_N */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06: PM_SLP_A_N */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07: SUSCLK */ + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), + /* GPP_V08: SLP_WLAN_N */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09: PM_SLP_S5_N */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10: LANPHYPC_R_N */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11: PM_SLP_LAN_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12: WAKE_N */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: GPP_V14_FORCEPR_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: GPP_V16_VCCST_EN */ + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), + /* GPP_V17: SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_V17, 1, PLTRST), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_H08: UART0_BUF_RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART0_BUF_TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_E02: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E02, NONE, PLTRST, LEVEL, INVERT), +}; + +/* Pad configuration in romstage */ +static const struct pad_config romstage_gpio_table[] = { + /* GPP_B16: GEN5_SSD_PWREN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + /* GPP_C00: GPP_C0_SMBCLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: GPP_C1_SMBDATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_E03: GEN5_SSD_RESET_N */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E19: FPMCU_PWREN */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/fatcat/variants/moonstone/hda_verb.c b/src/mainboard/google/fatcat/variants/moonstone/hda_verb.c new file mode 100644 index 0000000000..2f703b78ee --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/hda_verb.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ + 0x10ec12ac, /* Subsystem ID */ + 0x00000013, /* Number of jacks (NID entries) */ + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting-1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h new file mode 100644 index 0000000000..4fc0622f15 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h new file mode 100644 index 0000000000..cced66807a --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory.c b/src/mainboard/google/fatcat/variants/moonstone/memory.c new file mode 100644 index 0000000000..4637347562 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/memory.c @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 14, 12, 15, 11, 10, 8, 9, }, + .dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 }, + }, + .ddr1 = { + .dq0 = { 1, 3, 0, 2, 7, 4, 6, 5, }, + .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 }, + }, + .ddr2 = { + .dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 14, 13, 15, 12, 8, 11, 10, 9, }, + }, + .ddr3 = { + .dq0 = { 6, 5, 7, 4, 2, 3, 1, 0, }, + .dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 }, + }, + .ddr4 = { + .dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 }, + .dq1 = { 15, 14, 12, 13, 9, 11, 10, 8, }, + }, + .ddr5 = { + .dq0 = { 6, 5, 7, 4, 3, 1, 0, 2, }, + .dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 }, + }, + .ddr6 = { + .dq0 = { 9, 8, 11, 10, 14, 12, 13, 15, }, + .dq1 = { 6, 4, 5, 7, 1, 3, 0, 2 }, + }, + .ddr7 = { + .dq0 = { 0, 1, 2, 3, 7, 5, 6, 4, }, + .dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_A13 + * GPIO_MEM_CONFIG_1 GPP_D24 + * GPIO_MEM_CONFIG_2 GPP_B25 + * GPIO_MEM_CONFIG_3 GPP_B24 + */ + gpio_t spd_gpios[] = { + GPP_A13, + GPP_D24, + GPP_B25, + GPP_B24, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_C07 */ + return gpio_get(GPP_C07); +} diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk new file mode 100644 index 0000000000..da3bfa3b2d --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/memory/Makefile.mk @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/moonstone/memory src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-023 WT:C, H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 2(0b0010) Parts = MT62F2G32D4DS-020 WT:F, MT62F2G32D4DS-023 WT:C diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt new file mode 100644 index 0000000000..b90e238b88 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/memory/dram_id.generated.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/moonstone/memory src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H58G56BK7BX068 0 (0000) +MT62F1G32D2DS-023 WT:C 1 (0001) +MT62F2G32D4DS-020 WT:F 2 (0010) +H58G56CK8BX146 1 (0001) +MT62F2G32D4DS-023 WT:C 2 (0010) diff --git a/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f4a5069bb5 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/memory/mem_parts_used.txt @@ -0,0 +1,16 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H58G56BK7BX068 +MT62F1G32D2DS-023 WT:C +MT62F2G32D4DS-020 WT:F +H58G56CK8BX146 +MT62F2G32D4DS-023 WT:C diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb new file mode 100644 index 0000000000..624fa76f3b --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb @@ -0,0 +1,323 @@ +fw_config + field WIFI 2 2 + option WIFI_CNVI_7 0 + end + field AUDIO 3 5 + option AUDIO_UNKNOWN 0 + option AUDIO_ALC721_SNDW 1 + end +end + +chip soc/intel/pantherlake + + # The initial version temporarily uses the PTL-H, + # but the thermal design is based on the PTL-U. + # Apply PTL-U's thermal settings here to avoid thermal issues. + register "power_limits_config[PTL_H_1_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, + }" + + register "power_limits_config[PTL_H_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, + }" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_CAMERA + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port A1 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 Type-A Port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3.2 Type-A Port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1 + + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + }" + + # Enable CNVi Wi-Fi and Bluetooth + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0A] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C3 | TPM(cr50) | + #| I2C4 | Touchpad | + #| I2C5 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + /* Render OEM footer logo 100px above from the edge */ + .logo_bottom_margin = 100, + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "4" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP2 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + + device ref iaa off end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on end + end + end + end + end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref usb3_port2 on end + end + end + end + end + + device ref pcie_rp9 on + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end # Gen5 M.2 SSD + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion + device generic 0 on end + end + end # CNVi + + device ref cnvi_bluetooth on end + + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. + # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. + device ref i2c0 on end + device ref i2c3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)" + device i2c 50 on end + end + end # I2C3 + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2305"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" + # NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb. + register "generic.wake" = "GPE0_DW2_18" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 68 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)" + register "generic.wake" = "GPE0_DW2_18" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end # I2C4 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "generic.reset_delay_ms" = "150" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "generic.enable_delay_ms" = "6" + register "generic.enable_off_delay_ms" = "30" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end # I2C5 + device ref gspi0 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E22_IRQ)" + register "wake" = "GPE0_DW2_22" + register "has_power_resource" = "true" + register "use_gpio_for_status" = "true" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + register "enable_delay_ms" = "3" + device spi 0 on end + end + end + + device ref smbus on end + device ref hda on + probe AUDIO AUDIO_ALC721_SNDW + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" + register "alc711_address.class" = "MIPI_CLASS_SDCA" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721" + # SoundWire Link 3 ID 1 + device generic 3.1 on + probe AUDIO AUDIO_ALC721_SNDW + end + end + end + end + end + end +end diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c new file mode 100644 index 0000000000..4221a5bf8e --- /dev/null +++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +}