haswell NRI: Add pre-training steps
Implement pre-training steps, which consist of enabling ECC I/O and filling the WDB (Write Data Buffer, stores test patterns) through a magic LDAT port. Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64190 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
06d0ee4372
commit
9d0897a0bc
6 changed files with 273 additions and 0 deletions
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@ -10,5 +10,6 @@ romstage-y += memory_map.c
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romstage-y += raminit_main.c
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romstage-y += raminit_native.c
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romstage-y += reut.c
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romstage-y += setup_wdb.c
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romstage-y += spd_bitmunching.c
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romstage-y += timings_refresh.c
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@ -3,6 +3,7 @@
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <delay.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/haswell/chip.h>
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#include <northbridge/intel/haswell/haswell.h>
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@ -13,6 +14,39 @@
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#include "raminit_native.h"
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static enum raminit_status pre_training(struct sysinfo *ctrl)
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{
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/* Skip on S3 resume */
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if (ctrl->bootmode == BOOTMODE_S3)
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return RAMINIT_STATUS_SUCCESS;
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for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
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if (!rank_in_ch(ctrl, slot + slot, channel))
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continue;
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printk(RAM_DEBUG, "C%uS%u:\n", channel, slot);
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printk(RAM_DEBUG, "\tMR0: 0x%04x\n", ctrl->mr0[channel][slot]);
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printk(RAM_DEBUG, "\tMR1: 0x%04x\n", ctrl->mr1[channel][slot]);
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printk(RAM_DEBUG, "\tMR2: 0x%04x\n", ctrl->mr2[channel][slot]);
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printk(RAM_DEBUG, "\tMR3: 0x%04x\n", ctrl->mr3[channel][slot]);
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printk(RAM_DEBUG, "\n");
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}
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if (ctrl->is_ecc) {
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union mad_dimm_reg mad_dimm = {
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.raw = mchbar_read32(MAD_DIMM(channel)),
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};
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/* Enable ECC I/O */
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mad_dimm.ecc_mode = 1;
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mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
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/* Wait 4 usec after enabling the ECC I/O, needed by HW */
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udelay(4);
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}
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}
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setup_wdb(ctrl);
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return RAMINIT_STATUS_SUCCESS;
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}
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struct task_entry {
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enum raminit_status (*task)(struct sysinfo *);
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bool is_enabled;
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@ -26,6 +60,7 @@ static const struct task_entry cold_boot[] = {
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{ configure_mc, true, "CONFMC", },
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{ configure_memory_map, true, "MEMMAP", },
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{ do_jedec_init, true, "JEDECINIT", },
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{ pre_training, true, "PRETRAIN", },
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};
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/* Return a generic stepping value to make stepping checks simpler */
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@ -36,6 +36,13 @@
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#define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2))
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#define BASIC_VA_PAT_SPREAD_8 0x01010101
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#define WDB_CACHE_LINE_SIZE 8
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#define NUM_WDB_CL_MUX_SEEDS 3
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#define NUM_CADB_MUX_SEEDS 3
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/* ZQ calibration types */
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enum {
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ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
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@ -317,6 +324,23 @@ void reut_issue_mrs_all(
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enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
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void write_wdb_fixed_pat(
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const struct sysinfo *ctrl,
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const uint8_t patterns[],
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const uint8_t pat_mask[],
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uint8_t spread,
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uint16_t start);
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void write_wdb_va_pat(
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const struct sysinfo *ctrl,
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uint32_t agg_mask,
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uint32_t vic_mask,
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uint8_t vic_rot,
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uint16_t start);
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void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
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void setup_wdb(const struct sysinfo *ctrl);
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uint8_t get_rx_bias(const struct sysinfo *ctrl);
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uint8_t get_tCWL(uint32_t mem_clock_mhz);
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@ -335,6 +335,18 @@ union mcscheds_cbit_reg {
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uint32_t raw;
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};
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union reut_pat_cl_mux_lmn_reg {
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struct __packed {
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uint32_t l_data_select : 1; // Bits 0:0
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uint32_t en_sweep_freq : 1; // Bits 1:1
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uint32_t : 6; // Bits 7:2
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uint32_t l_counter : 8; // Bits 15:8
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uint32_t m_counter : 8; // Bits 23:16
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uint32_t n_counter : 8; // Bits 31:24
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};
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uint32_t raw;
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};
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union reut_pat_cadb_prog_reg {
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struct __packed {
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uint32_t addr : 16; // Bits 15:0
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@ -439,6 +451,39 @@ union reut_misc_odt_ctrl_reg {
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uint32_t raw;
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};
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union ldat_pdat_reg {
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struct __packed {
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uint32_t fast_addr : 12; // Bits 11:0
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uint32_t : 4; // Bits 15:12
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uint32_t addr_en : 1; // Bits 16:16
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uint32_t seq_en : 1; // Bits 17:17
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uint32_t pol_0 : 1; // Bits 18:18
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uint32_t pol_1 : 1; // Bits 19:19
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uint32_t cmd_a : 4; // Bits 23:20
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uint32_t cmd_b : 4; // Bits 27:24
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uint32_t cmd_c : 4; // Bits 31:28
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};
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uint32_t raw;
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};
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union ldat_sdat_reg {
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struct __packed {
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uint32_t bank_sel : 4; // Bits 3:0
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uint32_t : 1; // Bits 4:4
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uint32_t array_sel : 5; // Bits 9:5
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uint32_t cmp : 1; // Bits 10:10
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uint32_t replicate : 1; // Bits 11:11
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uint32_t dword : 4; // Bits 15:12
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uint32_t mode : 2; // Bits 17:16
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uint32_t mpmap : 6; // Bits 23:18
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uint32_t mpb_offset : 4; // Bits 27:24
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uint32_t stage_en : 1; // Bits 28:28
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uint32_t shadow : 2; // Bits 30:29
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uint32_t : 1; // Bits 31:31
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};
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uint32_t raw;
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};
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union mcscheds_dft_misc_reg {
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struct __packed {
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uint32_t wdar : 1; // Bits 0:0
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159
src/northbridge/intel/haswell/native_raminit/setup_wdb.c
Normal file
159
src/northbridge/intel/haswell/native_raminit/setup_wdb.c
Normal file
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@ -0,0 +1,159 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <northbridge/intel/haswell/haswell.h>
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#include <types.h>
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#include "raminit_native.h"
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static void ldat_write_cacheline(
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const struct sysinfo *const ctrl,
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const uint8_t chunk,
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const uint16_t start,
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const uint64_t data)
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{
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for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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if (!does_ch_exist(ctrl, channel))
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continue;
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/*
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* Do not do a 64-bit write here. The register is not aligned
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* to a 64-bit boundary, which could potentially cause issues.
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*/
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mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 0), data & UINT32_MAX);
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mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 1), data >> 32);
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/*
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* Set REPLICATE = 0 as you don't want to replicate the data.
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* Set BANK_SEL to the chunk you want to write the 64 bits to.
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* Set ARRAY_SEL = 0 (the MC WDB) and MODE = 1.
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*/
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const union ldat_sdat_reg ldat_sdat = {
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.bank_sel = chunk,
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.mode = 1,
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};
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mchbar_write32(QCLK_ch_LDAT_SDAT(channel), ldat_sdat.raw);
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/*
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* Finally, write the PDAT register indicating which cacheline
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* of the WDB you want to write to by setting FAST_ADDR field
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* to one of the 64 cache lines. Also set CMD_B in the PDAT
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* register to 4'b1000, indicating that this is a LDAT write.
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*/
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const union ldat_pdat_reg ldat_pdat = {
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.fast_addr = MIN(start, 0xfff),
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.cmd_b = 8,
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};
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mchbar_write32(QCLK_ch_LDAT_PDAT(channel), ldat_pdat.raw);
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}
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}
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static void clear_ldat_mode(const struct sysinfo *const ctrl)
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{
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for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
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mchbar_write32(QCLK_ch_LDAT_SDAT(channel), 0);
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}
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void write_wdb_fixed_pat(
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const struct sysinfo *const ctrl,
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const uint8_t patterns[],
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const uint8_t pat_mask[],
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const uint8_t spread,
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const uint16_t start)
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{
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for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
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uint64_t data = 0;
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for (uint8_t b = 0; b < 64; b++) {
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const uint8_t beff = b % spread;
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const uint8_t burst = patterns[pat_mask[beff]];
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if (burst & BIT(chunk))
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data |= 1ULL << b;
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}
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ldat_write_cacheline(ctrl, chunk, start, data);
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}
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clear_ldat_mode(ctrl);
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}
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static inline uint32_t rol_u32(const uint32_t val)
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{
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return (val << 1) | ((val >> 31) & 1);
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}
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void write_wdb_va_pat(
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const struct sysinfo *const ctrl,
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const uint32_t agg_mask,
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const uint32_t vic_mask,
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const uint8_t vic_rot,
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const uint16_t start)
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{
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static const uint8_t va_mask_to_compressed[4] = {0xaa, 0xc0, 0xcc, 0xf0};
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uint32_t v_mask = vic_mask;
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uint32_t a_mask = agg_mask;
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for (uint8_t v = 0; v < vic_rot; v++) {
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uint8_t compressed[32] = {0};
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/* Iterate through all 32 bits and create a compressed version of cacheline */
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for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++) {
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const uint8_t vic = !!(v_mask & BIT(b));
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const uint8_t agg = !!(a_mask & BIT(b));
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const uint8_t index = !vic << 1 | agg << 0;
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compressed[b] = va_mask_to_compressed[index];
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}
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for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
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uint32_t data = 0;
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for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++)
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data |= !!(compressed[b] & BIT(chunk)) << b;
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const uint64_t data64 = (uint64_t)data << 32 | data;
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ldat_write_cacheline(ctrl, chunk, start + v, data64);
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}
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v_mask = rol_u32(v_mask);
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a_mask = rol_u32(a_mask);
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}
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clear_ldat_mode(ctrl);
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}
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void program_wdb_lfsr(const struct sysinfo *ctrl, const bool cleanup)
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{
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/* Cleanup LFSR seeds are sequential */
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const uint32_t cleanup_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xaaaaaa, 0xcccccc, 0xf0f0f0 };
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const uint32_t regular_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xa10ca1, 0xef0d08, 0xad0a1e };
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const uint32_t *seeds = cleanup ? cleanup_seeds : regular_seeds;
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for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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if (!does_ch_exist(ctrl, channel))
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continue;
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for (uint8_t i = 0; i < NUM_WDB_CL_MUX_SEEDS; i++) {
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mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_RD_x(channel, i), seeds[i]);
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mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_WR_x(channel, i), seeds[i]);
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}
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}
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}
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void setup_wdb(const struct sysinfo *ctrl)
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{
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const uint32_t amask[9] = {
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0x86186186, 0x18618618, 0x30c30c30,
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0xa28a28a2, 0x8a28a28a, 0x14514514,
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0x28a28a28, 0x92492492, 0x24924924,
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};
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const uint32_t vmask = 0x41041041;
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/* Fill first 8 entries with simple 2-LFSR VA pattern */
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write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
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/* Fill next 54 entries with 3-LFSR VA pattern */
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for (uint8_t a = 0; a < ARRAY_SIZE(amask); a++)
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write_wdb_va_pat(ctrl, amask[a], vmask, 6, 8 + a * 6);
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program_wdb_lfsr(ctrl, false);
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for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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if (!does_ch_exist(ctrl, channel))
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continue;
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const union reut_pat_cl_mux_lmn_reg wdb_cl_mux_lmn = {
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.en_sweep_freq = 1,
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.l_counter = 1,
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.m_counter = 1,
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.n_counter = 10,
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};
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mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_LMN(channel), wdb_cl_mux_lmn.raw);
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}
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}
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@ -94,6 +94,11 @@
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#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
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#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
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#define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x) _MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
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#define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x) _MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
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#define REUT_ch_PAT_WDB_CL_MUX_LMN(ch) _MCMAIN_C(0x4078, ch)
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#define SC_WR_ADD_DELAY_ch(ch) _MCMAIN_C(0x40d0, ch)
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#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
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@ -110,6 +115,10 @@
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#define MC_INIT_STATE_ch(ch) _MCMAIN_C(0x42a0, ch)
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#define TC_SRFTP_ch(ch) _MCMAIN_C(0x42a4, ch)
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#define QCLK_ch_LDAT_PDAT(ch) _MCMAIN_C(0x42d0, ch)
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#define QCLK_ch_LDAT_SDAT(ch) _MCMAIN_C(0x42d4, ch)
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#define QCLK_ch_LDAT_DATA_IN_x(ch, x) _MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
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#define REUT_GLOBAL_ERR 0x4804
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#define REUT_ch_SEQ_CFG(ch) (0x48a8 + 8 * (ch))
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