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UPSTREAM: nb/intel/*/graphic_init: use sizeof instead of hardcoding edid size

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16964
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I2b8c4ef75cca9f9d5251789cda4187a02076b69d
Reviewed-on: https://chromium-review.googlesource.com/397910
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Arthur Heymans 2016-10-10 17:49:00 +02:00 • committed by chrome-bot
commit 9ca2c0d000
6 changed files with 16 additions and 8 deletions
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9
src/northbridge/intel/gm45/gma.c
View file

@ -99,7 +99,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
for (i = 0; i <= 0x18; i++)
vga_cr_write(i, cr[i]);
intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data,
sizeof(edid_data));
decode_edid(edid_data,
sizeof(edid_data), &edid);
mode = &edid.mode;
@ -410,7 +411,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
udelay(1);
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128);
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data,
sizeof(edid_data));
intel_gmbus_stop(mmio + GMBUS0);
decode_edid(edid_data,
sizeof(edid_data), &edid);
@ -644,7 +646,8 @@ static u8 vga_connected(u8 *mmio)
{
u8 vga_edid[128];
u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128);
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid,
sizeof(vga_edid));
intel_gmbus_stop(mmio + GMBUS0);
for (int i = 0; i < 8; i++) {
if (vga_edid[i] != header[i]) {

3
src/northbridge/intel/i945/gma.c
View file

@ -103,7 +103,8 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
"i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
(void *)pgfx, pmmio, piobase, pphysbase);
intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data,
sizeof(edid_data));
decode_edid(edid_data, sizeof(edid_data), &edid);
mode = &edid.mode;

3
src/northbridge/intel/nehalem/gma.c
View file

@ -696,7 +696,8 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
power_port(mmio);
intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data,
sizeof(edid_data));
intel_gmbus_stop(mmio + PCH_GMBUS0);
decode_edid(edid_data,
sizeof(edid_data), &edid);

3
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
View file

@ -202,7 +202,8 @@ int i915lightup_ivy(const struct i915_gpu_controller_info *info,
enable_port(mmio);
intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data,
sizeof(edid_data));
intel_gmbus_stop(mmio + PCH_GMBUS0);
decode_edid(edid_data,
sizeof(edid_data), &edid);

3
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
View file

@ -186,7 +186,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
power_port(mmio);
intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data,
sizeof(edid_data));
decode_edid(edid_data, sizeof(edid_data), &edid);
mode = &edid.mode;

3
src/northbridge/intel/x4x/gma.c
View file

@ -119,7 +119,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
udelay(1);
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128);
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data,
sizeof(edid_data));
intel_gmbus_stop(mmio + GMBUS0);
decode_edid(edid_data,
sizeof(edid_data), &edid);