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exynos5420: set L2ACTLR parameters for A15 cores

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This patch does the following for the A15 cores:
- Disable clean/evict push to external
- Enable hazard detect timout
- Prevent gating the L2 logic clock

This is ported from https://gerrit.chromium.org/gerrit/#/c/60154

Signed-off-by: David Hendricks <dhendrix@chromium.org>

BUG=none
BRANCH=none
TEST=built and booted on Pit, seems as stable as before...

Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
Reviewed-on: https://gerrit.chromium.org/gerrit/64862
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2013-08-06 18:05:55 -07:00 • committed by ChromeBot
commit 9c2311f98c
1 changed files with 16 additions and 0 deletions
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16
src/cpu/samsung/exynos5420/cpu.c
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@ -198,4 +198,20 @@ void exynos5420_config_l2_cache(void)
*/
val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2);
write_l2ctlr(val);
val = read_l2actlr();
/* L2ACTLR[3]: Disable clean/evict push to external */
val |= (1 << 3);
/* L2ACTLR[7]: Enable hazard detect timeout for A15 */
val |= (1 << 7);
/* L2ACTLR[27]: Prevents stopping the L2 logic clock */
val |= (1 << 27);
write_l2actlr(val);
/* Read the l2 control register to force things to take effect? */
val = read_l2ctlr();
}