From 9b91d50fc1797e4d84ddfc7c18085de3a14c3f7e Mon Sep 17 00:00:00 2001 From: Kilian Krause Date: Tue, 27 May 2025 15:29:11 +0200 Subject: [PATCH] mb/siemens/mc_rpl1: Add GPIO configuration Provide a valid GPIO configuration based on the mainboard wiring. BUG=none TEST=Checked output of verbose GPIO debug messages. Change-Id: I75570acf2bb11a99b99fe70b9d639837daee125c Signed-off-by: Kilian Krause Reviewed-on: https://review.coreboot.org/c/coreboot/+/87913 Reviewed-by: Werner Zeh Reviewed-by: Mario Scheithauer Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_rpl/Makefile.mk | 2 - src/mainboard/siemens/mc_rpl/early_gpio.c | 148 ---------- src/mainboard/siemens/mc_rpl/gpio.c | 276 ------------------ .../mc_rpl/variants/mc_rpl1/Makefile.mk | 4 + .../mc_rpl/variants/mc_rpl1/early_gpio.c | 26 ++ .../siemens/mc_rpl/variants/mc_rpl1/gpio.c | 81 +++++ 6 files changed, 111 insertions(+), 426 deletions(-) delete mode 100644 src/mainboard/siemens/mc_rpl/early_gpio.c delete mode 100644 src/mainboard/siemens/mc_rpl/gpio.c create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c create mode 100644 src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk index 013a8f603e..e6c0dd62d1 100644 --- a/src/mainboard/siemens/mc_rpl/Makefile.mk +++ b/src/mainboard/siemens/mc_rpl/Makefile.mk @@ -3,9 +3,7 @@ subdirs-y += spd bootblock-y += bootblock.c -bootblock-y += early_gpio.c -ramstage-y += gpio.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c romstage-y += memory.c diff --git a/src/mainboard/siemens/mc_rpl/early_gpio.c b/src/mainboard/siemens/mc_rpl/early_gpio.c deleted file mode 100644 index c3b2e2a47c..0000000000 --- a/src/mainboard/siemens/mc_rpl/early_gpio.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* WWAN_RST# (updated in ramstage) */ - PAD_CFG_GPO(GPP_F14, 0, DEEP), - /* WWAN_PERST_L (updated in ramstage) */ - PAD_CFG_GPO(GPP_C5, 0, DEEP), - /* WWAN_FCPO_L (updated in romstage) */ - PAD_CFG_GPO(GPP_F15, 0, DEEP), - /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), - /* SMB_CLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* SMB_DATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - - /* EC_IN_RW */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), - - /* x4 PCIE slot 1 RESET */ - PAD_CFG_GPO(GPP_F10, 0, PLTRST), - - /* Support external source clock via OEB6 and OEB7 */ - /* SRCCLK_OEB6 for built-in LAN */ - PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF2), - /* SRCCLK_OEB7 for x4 slot */ - PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), - - /* CPU PCIe VGPIO for RP0 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1), - - /* CPU PCIe vGPIO for RP1 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1), - - /* CPU PCIe vGPIO for RP2 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), - - /* CPU PCIe vGPIO for RP3 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), - - /*_TPM_*/ - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), - /* F16 : GSPI1_CS0N */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), - /* F11 : GSPI1_CLK */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), - /* F13 : GSPI1_MISO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), - /* F12 : GSPI1_MOSI */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), -}; - -static const struct pad_config early_uart_gpio_table[] = { - /* UART0 RX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* UART0 TX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), -}; - -void variant_configure_early_gpio_pads(void) -{ - if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) - gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); - - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} diff --git a/src/mainboard/siemens/mc_rpl/gpio.c b/src/mainboard/siemens/mc_rpl/gpio.c deleted file mode 100644 index d1ed7c7df1..0000000000 --- a/src/mainboard/siemens/mc_rpl/gpio.c +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when - eSPI is enabled */ - - /* SSD1_PWREN CPU SSD1 */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), - /* SSD1_RESET CPU SSD1 */ - PAD_CFG_GPO(GPP_F20, 1, PLTRST), - /* BT_RF_KILL_N */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), - /* WLAN RST# */ - PAD_CFG_GPO(GPP_H2, 1, PLTRST), - /* WIFI_WAKE_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), - /* x4 PCIE slot1 PWREN */ - PAD_CFG_GPO(GPP_H17, 0, PLTRST), - /* x4 PCIE slot 1 RESET */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - /* Retimer Force Power */ - PAD_CFG_GPO(GPP_E4, 0, PLTRST), - /* PEG Slot RST# */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), - /* M.2 SSD_2 Reset */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), - /* CAM_STROBE */ - PAD_CFG_GPO(GPP_B18, 0, PLTRST), - /* Audio Codec INT N */ - PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), - /* TCH PAD Power EN */ - PAD_CFG_GPO(GPP_F7, 1, PLTRST), - /* THC1 SPI2 RST# */ - PAD_CFG_GPO(GPP_F17, 1, PLTRST), - /* THC1_SPI2_INTB */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), - /* THC1_SPI2_INTB */ - PAD_CFG_GPI(GPP_E17, NONE, PLTRST), - /* EC_SLP_S0_CS_N */ - PAD_CFG_GPO(GPP_F9, 1, PLTRST), - /* DISP_AUX_N_BIAS_GPIO */ - PAD_CFG_GPO(GPP_E23, 1, PLTRST), - /* WWAN WAKE N*/ - PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), - /* WWAN_DISABLE_N */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), - /* WWAN_RST# */ - PAD_CFG_GPO(GPP_F14, 1, DEEP), - /* WWAN_FCP_OFF_N */ - PAD_CFG_GPO(GPP_F15, 1, DEEP), - /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), - /* WWAN_PERST# */ - PAD_CFG_GPO(GPP_C5, 1, DEEP), - /* PEG_SLOT_WAKE_N */ - PAD_CFG_GPI(GPP_A20, NONE, PLTRST), - /* CAM CONN1 CLKEN */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), - /* CPU SSD2 PWREN */ - PAD_CFG_GPO(GPP_C2, 1, PLTRST), - /* CPU SSD2 RST# */ - PAD_CFG_GPO(GPP_H1, 1, PLTRST), - /* Sata direct Power */ - PAD_CFG_GPO(GPP_B4, 1, PLTRST), - /* M.2_PCH_SSD_PWREN */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), - - /* CAM1_RST */ - PAD_CFG_GPO(GPP_R5, 1, PLTRST), - /* CAM2_RST */ - PAD_CFG_GPO(GPP_E15, 1, PLTRST), - /* CAM1_PWR_EN */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), - /* CAM2_PWR_EN */ - PAD_CFG_GPO(GPP_E16, 1, PLTRST), - /* M.2_SSD_PDET_R */ - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - /* THC0 SPI1 CLK */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), - /* THC0 SPI1 IO 1 */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), - /* THC0 SPI1 IO 2 */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), - /* THC0 SPI IO 3 */ - PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), - /* THC1 SPI1 RSTB */ - PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), - /* UART_RX(1) */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* UART_RX(2) */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* UART_RX(4) */ - PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), - /* UART_RX(5) */ - PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), - /* UART_RX(6) */ - PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), - - /* UART_TX(1) */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - /* UART_TX(2) */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - /* UART_TX(4) */ - PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), - /* UART_TX(5) */ - PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), - /* UART_TX(6) */ - PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), - - /* UART_RTS(1) */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - /* UART_RTS(2) */ - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), - /* UART_RTS(4) */ - PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), - /* UART_RTS(5) */ - PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), - /* UART_RTS(6) */ - PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), - - /* UART_CTS(1) */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), - /* UART_CTS(2) */ - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), - /* UART_CTS(4) */ - PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), - /* UART_CTS(5) */ - PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), - /* UART_CTS(6) */ - PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), - - /* SPI_MOSI(1) */ - PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), - /* SPI_MOSI(2) */ - PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), - - /* SPI_MIS0(1) */ - PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), - /* SPI_MIS0(2) */ - PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), - - /* SPI_CLK(1) */ - PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), - /* SPI_CLK(2) */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), - - /* SPI_CS(0, 1) */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), - /* SPI_CS(1, 0) */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), - /* SPI_CS(2, 0) */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), - - /* I2C_SCL(0) */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* I2C_SCL(2) */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), - /* I2C_SCL(3) */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), - - /* I2C_SDA(0) */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* I2C_SDA(2) */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), - /* I2C_SDA(3) */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), - - /* I2S0_SCLK */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* I2S0_SFRM */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* I2S0_TXD */ - PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), - /* I2S0_RXD */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - - /* I2S_MCLK1_OUT */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - /* I2S_MCLK2_INOUT */ - PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), - - /* SNDW1_CLK */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), - /* SNDW1_DATA */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), - /* SNDW2_CLK */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), - /* SNDW2_DATA */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), - /* SNDW3_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), - /* SNDW3_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), - /* SNDW4_CLK */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), - /* SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - - /* SMB_CLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* SMB_DATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - - /* SATA DEVSLP */ - PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4), - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5), - - /* SATA LED pin */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - - /* USB2 OC0 pins */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* USB2 OC3 pins */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - - /* GPIO pin for PCIE SRCCLKREQB */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_NC(GPP_D8, NONE), - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - - /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), - - /* HPD_1 (E14) and HPD_2 (A18) pins */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), - - /* IMGCLKOUT */ - PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - /* H23 : CLKREQ5_WWAN_N */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), - - /* A21 : HDMI CRLS CTRLCLK */ - PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), - /* A22 : HDMI CRLS CTRLDATA */ - PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT) -}; - -void variant_configure_gpio_pads(void) -{ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; -DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk new file mode 100644 index 0000000000..45c478178a --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += early_gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c new file mode 100644 index 0000000000..c5c19ddabc --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/early_gpio.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPI(GPP_F11, NONE, DEEP), + PAD_CFG_GPI(GPP_F12, NONE, DEEP), + PAD_CFG_GPI(GPP_F13, NONE, DEEP), + PAD_CFG_GPI(GPP_F14, NONE, DEEP), +}; + +static const struct pad_config early_uart_gpio_table[] = { + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF2), /* UART2_RXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF2), /* UART2_TXD */ +}; + +void variant_configure_early_gpio_pads(void) +{ + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c new file mode 100644 index 0000000000..8b10b57040 --- /dev/null +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when + eSPI is enabled */ + + /* Community 0 - Gpio Group GPP_B */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4), + PAD_CFG_GPI(GPP_B23, NONE, PLTRST), + + /* Community 0 - Gpio Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* eSPI */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* eSPI */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* eSPI */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* eSPI */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* eSPI */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* USB2 OC1 pin */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB2 OC2 pin */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* USB2 OC3 pin */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* eSPI */ + + /* Community 1 - Gpio Group GPP_H */ + PAD_CFG_GPI(GPP_H0, NONE, PLTRST), + PAD_CFG_GPI(GPP_H1, NONE, PLTRST), + PAD_CFG_GPI(GPP_H2, NONE, PLTRST), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C1_SDA */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C1_SCL */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0_RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* PCIE_XCLKREQ4 */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), /* PCIE_XCLKREQ5 */ + + /* Community 1 - Gpio Group GPP_D */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_XCLKREQ0 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_XCLKREQ1 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_XCLKREQ2 */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* PCIE_XCLKREQ3 */ + PAD_CFG_GPI(GPP_D10, NONE, PLTRST), + PAD_CFG_GPI(GPP_D12, NONE, PLTRST), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* UART1_TXD */ + + /* Community 2 - Gpio Group GPD */ + PAD_CFG_GPI(GPD7, NONE, PLTRST), + + /* Community 4 - Gpio Group GPP_C */ + PAD_CFG_GPI(GPP_C2, NONE, PLTRST), + PAD_CFG_GPI(GPP_C5, NONE, DEEP), + + /* Community 4 - Gpio Group GPP_F */ + PAD_CFG_GPI(GPP_F0, NONE, PLTRST), + PAD_CFG_GPO(GPP_F4, 0, PLTRST), + PAD_CFG_GPI(GPP_F7, NONE, PLTRST), + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* PCIE_XCLKREQ6 */ + + /* Community 4 - Gpio Group GPP_E */ + PAD_CFG_GPI(GPP_E6, NONE, PLTRST), + PAD_CFG_GPI(GPP_E8, NONE, PLTRST), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2 OC0 pin */ + PAD_CFG_GPI(GPP_E14, NONE, PLTRST), + PAD_CFG_GPI(GPP_E19, NONE, PLTRST), + PAD_CFG_GPI(GPP_E21, NONE, PLTRST), + PAD_CFG_GPO(GPP_E22, 0, PLTRST), + + /* Community 5 - Gpio Group GPP_R */ + PAD_CFG_GPI(GPP_R2, NONE, PLTRST), + +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +}