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mb/lenovo/*/romstage: Use macros instead of magic numbers

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Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead. Also removed FDD from l520
romstage (original value, 0x3c0c, means that FDD_LPC_EN was also
enabled).

Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Peter Lemenkov 2018-10-09 13:09:07 +02:00 • committed by Patrick Georgi
commit 9b7ae2f3fc
3 changed files with 19 additions and 14 deletions
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14
src/mainboard/lenovo/l520/romstage.c
View file

@ -25,11 +25,15 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse, LPT */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
LPT_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701);
}
void mainboard_rcba_config(void)

17
src/mainboard/lenovo/s230u/romstage.c
View file

@ -32,18 +32,17 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */
pci_write_config32(
PCI_DEV(0, 0x1f, 0), 0x98,
PCH_LPC_DEV, LGMR,
CONFIG_EC_BASE_ADDRESS | 1);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0);
pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0);
/* Enable external USB port power. */
if (IS_ENABLED(CONFIG_USBDEBUG))
@ -53,7 +52,7 @@ void pch_enable_lpc(void)
void mainboard_rcba_config(void)
{
/* Disable devices. */
RCBA32(0x3414) = 0x00000020;
RCBA32(BUC) = 0x00000020;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 },