From 9aa69fd43d77f5f7acdc9f361016c595dd16104e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 6 Nov 2014 09:58:07 -0600 Subject: [PATCH] timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation. BUG=None BRANCH=None TEST=Built Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/228190 Reviewed-by: Furquan Shaikh Reviewed-by: Julius Werner --- src/arch/x86/boot/acpi.c | 4 ---- src/cpu/intel/haswell/romstage.c | 3 --- src/include/timestamp.h | 11 ++++++----- src/lib/selfboot.c | 4 ---- src/mainboard/emulation/qemu-x86/romstage.c | 4 ++-- src/mainboard/google/butterfly/romstage.c | 16 ++++++---------- src/mainboard/google/cosmos/romstage.c | 16 ++++++---------- src/mainboard/google/daisy/romstage.c | 12 ++---------- src/mainboard/google/link/romstage.c | 16 ++++++---------- src/mainboard/google/parrot/romstage.c | 16 ++++++---------- src/mainboard/google/peach_pit/romstage.c | 12 ++---------- src/mainboard/google/stout/romstage.c | 16 ++++++---------- src/mainboard/google/veyron_jerry/romstage.c | 4 ++-- src/mainboard/intel/emeraldlake2/romstage.c | 16 ++++++---------- src/mainboard/samsung/lumpy/romstage.c | 15 +++++---------- src/mainboard/samsung/stumpy/romstage.c | 16 ++++++---------- src/soc/intel/broadwell/bootblock/pch.c | 3 +-- src/southbridge/intel/bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/lynxpoint/bootblock.c | 3 +-- 19 files changed, 64 insertions(+), 126 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index eac1a50ed4..a875bee320 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -33,9 +33,7 @@ #include #include #include -#if CONFIG_COLLECT_TIMESTAMPS #include -#endif /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -777,9 +775,7 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_ACPI_WAKE_JUMP); -#endif acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index ffb3ae47f0..fee928dd2d 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -199,13 +199,10 @@ void romstage_common(const struct romstage_params *params) int wake_from_s3; struct romstage_handoff *handoff; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); timestamp_early_init(base_time); -#endif - timestamp_add_now(TS_START_ROMSTAGE); if (params->bist == 0) diff --git a/src/include/timestamp.h b/src/include/timestamp.h index e3e9450784..9bd8ea903a 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -94,11 +94,12 @@ void timestamp_sync(void); /* Implemented by the architecture code */ uint64_t timestamp_get(void); #else -#define timestamp_early_init(base) -#define timestamp_init(base) -#define timestamp_add(id, time) -#define timestamp_add_now(id) -#define timestamp_sync() +static inline void timestamp_early_init(uint64_t base) { } +static inline void timestamp_init(uint64_t base) { } +static inline void timestamp_add(enum timestamp_id id, uint64_t ts_time) { } +static inline void timestamp_add_now(enum timestamp_id id) { } +static inline void timestamp_sync(void) { } +static inline uint64_t timestamp_get(void) { return 0; } #endif #endif diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 84c1574d6a..995f1ca180 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -30,9 +30,7 @@ #include #include #include -#if CONFIG_COLLECT_TIMESTAMPS #include -#endif /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR @@ -538,9 +536,7 @@ void selfboot(void *entry) printk(BIOS_DEBUG, "Jumping to boot code at %p\n", entry); post_code(POST_ENTER_ELF_BOOT); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_SELFBOOT_JUMP); -#endif /* Before we go off to run the payload, see if * we stayed within our bounds. diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index 3faf947e00..c80a25de91 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -49,10 +49,10 @@ void main(unsigned long bist) //dump_pci_devices(); cbmem_was_initted = !cbmem_initialize(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(rdtsc()); timestamp_add_now(TS_START_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index b659b8a7e4..e33415ef54 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -118,14 +118,13 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif + struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -173,9 +172,7 @@ void main(unsigned long bist) ddr_refresh_rate_config: 2, /* Force double refresh rate */ }; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -240,14 +237,13 @@ void main(unsigned long bist) post_code(0x3a); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3c); rcba_config(); @@ -287,13 +283,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index 76184afc6e..f16d782a10 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -37,34 +37,30 @@ void main(void) { void *entry; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif console_init(); -#if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); -#endif + sdram_init(); -#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); -#endif + mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); dcache_mmu_enable(); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif entry = vboot2_load_ramstage(); @@ -76,8 +72,8 @@ void main(void) if (entry == (void *)-1) die("failed to load ramstage\n"); } -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif + stage_exit(entry); } diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index e641963bfd..5463fe4ff3 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -144,14 +144,12 @@ void main(void) struct mem_timings *mem; void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ @@ -161,14 +159,12 @@ void main(void) exception_init(); setup_power(is_resume); -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + setup_memory(mem, is_resume); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif /* This needs to happen on normal boots and on resume. */ trustzone_init(); @@ -186,18 +182,14 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); -#endif entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif stage_exit(entry); } diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f53df93bf..6e07ee0843 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -154,14 +154,13 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif + struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -208,9 +207,7 @@ void main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -282,14 +279,13 @@ void main(unsigned long bist) post_code(0x3a); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3c); rcba_config(); @@ -329,13 +325,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 82675017d7..f33852b081 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -119,14 +119,13 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif + struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -173,9 +172,7 @@ void main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -240,14 +237,13 @@ void main(unsigned long bist) post_code(0x3a); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3c); rcba_config(); @@ -287,13 +283,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 37c966290b..d997e34d74 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -228,14 +228,13 @@ void main(void) void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); int power_init_failed; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif + exynos5420_config_smp(); power_init_failed = setup_power(is_resume); @@ -253,14 +252,11 @@ void main(void) /* re-initialize PMIC I2C channel after (re-)setting system clocks */ i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ -#if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); -#endif + setup_memory(&mem_timings, is_resume); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif primitive_mem_test(); @@ -282,19 +278,15 @@ void main(void) cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); -#endif entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); simple_spi_test(); -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif stage_exit(entry); } diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index b7c41aa7da..48ff7b0834 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -158,14 +158,13 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif + struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -217,9 +216,7 @@ void main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -289,14 +286,13 @@ void main(unsigned long bist) post_code(0x3a); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_init(); @@ -344,13 +340,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 8294aef0e6..958b4dfb58 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -110,8 +110,8 @@ void main(void) if (entry == (void *)-1) die("failed to load ramstage\n"); } -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif + stage_exit(entry); } diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 7f97ff77cb..7a1d32ba22 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -170,14 +170,13 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif + struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, @@ -222,9 +221,7 @@ void main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -288,14 +285,13 @@ void main(unsigned long bist) post_code(0x3a); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_init(); @@ -341,13 +337,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 316a6d65d3..0d7802933a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -137,14 +137,12 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif struct pei_data pei_data = { .mchbar = DEFAULT_MCHBAR, @@ -195,9 +193,7 @@ void main(unsigned long bist) spd_blob *spd_data; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -310,14 +306,13 @@ void main(unsigned long bist) post_code(0x39); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3a); /* Perform some initialization that must run before stage2 */ early_pch_init(); @@ -361,13 +356,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 59b835fbc9..6f138b8c63 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -173,14 +173,13 @@ void main(unsigned long bist) u32 pm1_cnt; u16 pm1_sts; -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); -#endif + struct pei_data pei_data = { mchbar: DEFAULT_MCHBAR, dmibar: DEFAULT_DMIBAR, @@ -223,9 +222,7 @@ void main(unsigned long bist) }, }; -#if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); -#endif if (bist == 0) enable_lapic(); @@ -315,14 +312,13 @@ void main(unsigned long bist) post_code(0x39); pei_data.boot_mode = boot_mode; -#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); -#endif + sdram_initialize(&pei_data); -#if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); -#endif + post_code(0x3a); /* Perform some initialization that must run before stage2 */ early_pch_init(); @@ -365,13 +361,13 @@ void main(unsigned long bist) #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); -#endif + #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index e23939bde4..b163f103f0 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -84,9 +84,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 85a940e2de..afd6280180 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -86,9 +86,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 96291189cd..89f23c7e17 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc();