From 9a60da5297ba8922be03e82dc8b186355cebfc3a Mon Sep 17 00:00:00 2001 From: Wentao Qin Date: Fri, 7 Feb 2025 11:26:41 +0800 Subject: [PATCH] mb/google/skywalker: Enable ChromeOS EC 1. Configure ChromeOS EC. 2. Pass GPIO_EC_AP_INT_ODL to the payload. 3. Initialize SPI bus 0 for ChromeOS EC control. BUG=b:391957745 BRANCH=none TEST=check boot log Signed-off-by: Wentao Qin Change-Id: Id3d53dfa8e1fdee5f04f01197592d31fee146299 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87358 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/mainboard/google/skywalker/Kconfig | 10 ++++++++++ src/mainboard/google/skywalker/bootblock.c | 2 ++ src/mainboard/google/skywalker/chromeos.c | 8 ++++++++ src/mainboard/google/skywalker/gpio.h | 4 ++++ src/mainboard/google/skywalker/reset.c | 5 ++++- 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig index cf9c69f9b5..ddc20e20f3 100644 --- a/src/mainboard/google/skywalker/Kconfig +++ b/src/mainboard/google/skywalker/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_SKYWALKER_COMMON if BOARD_GOOGLE_SKYWALKER_COMMON config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT select VBOOT_MOCK_SECDATA @@ -18,9 +19,13 @@ config BOARD_SPECIFIC_OPTIONS select SOC_MEDIATEK_MT8189 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI config MAINBOARD_DIR string @@ -35,4 +40,9 @@ config MAINBOARD_PART_NUMBER config BOOT_DEVICE_SPI_FLASH_BUS int default 7 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x0 + endif diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c index 71c3dfc418..b090924b77 100644 --- a/src/mainboard/google/skywalker/bootblock.c +++ b/src/mainboard/google/skywalker/bootblock.c @@ -13,6 +13,8 @@ static void usb3_hub_reset(void) void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/skywalker/chromeos.c b/src/mainboard/google/skywalker/chromeos.c index b779fe7bce..79b5d42b90 100644 --- a/src/mainboard/google/skywalker/chromeos.c +++ b/src/mainboard/google/skywalker/chromeos.c @@ -1,14 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include +#include #include #include "gpio.h" +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { {GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"}, + {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/skywalker/gpio.h b/src/mainboard/google/skywalker/gpio.h index 74d9b04154..da1622edc0 100644 --- a/src/mainboard/google/skywalker/gpio.h +++ b/src/mainboard/google/skywalker/gpio.h @@ -7,5 +7,9 @@ #define GPIO_XHCI_INIT_DONE GPIO(GBE_MDC) #define GPIO_USB3_HUB_RST_L GPIO(GPIO07) +#define GPIO_EC_AP_INT_ODL GPIO(GBE_MDIO) +#define GPIO_AP_EC_WARM_RST_REQ GPIO(GBE_AUX_PPS0) + +void setup_chromeos_gpios(void); #endif diff --git a/src/mainboard/google/skywalker/reset.c b/src/mainboard/google/skywalker/reset.c index 1a4b15682b..e50cf3bbfa 100644 --- a/src/mainboard/google/skywalker/reset.c +++ b/src/mainboard/google/skywalker/reset.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +#include #include +#include "gpio.h" + void do_board_reset(void) { - /* TODO: add reset function when gpio is ready */ + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); }