From 99b6ff25d4989e3b58606d2ae328ee4679bfb725 Mon Sep 17 00:00:00 2001 From: Vince Liu Date: Thu, 9 Jan 2025 13:38:31 +0800 Subject: [PATCH] soc/mediatek/mt8189: Add MTK FSP loader in ramstage To support the MTK firmware support package (FSP), reserve a 2MB region in DRAM for loading `mtk_fsp_ramstage.elf` during ramstage. BUG=b:379008996 BRANCH=none TEST=build passed Signed-off-by: Vince Liu Change-Id: If153d9746bea8c7faa8f9787029b44192c18899d Reviewed-on: https://review.coreboot.org/c/coreboot/+/87813 Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8189/Makefile.mk | 9 +++++++++ src/soc/mediatek/mt8189/include/soc/memlayout.ld | 1 + 2 files changed, 10 insertions(+) diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index b8ff8bff29..7f9b86834b 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -40,6 +40,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += ../common/mt6315.c mt6315.c ramstage-y += ../common/mt6359p.c mt6359p.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/mtk_fsp.c ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c ramstage-y += ../common/pmif_spi.c pmif_spi.c ramstage-y += ../common/pmif_spmi.c pmif_spmi.c @@ -81,3 +82,11 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mediatek/gen-bl-img.py mt8189 sf $< $@ endif + +FSP_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage +$(FSP_CBFS)-file := $(MT8189_BLOB_DIR)/mtk_fsp_ramstage.elf +$(FSP_CBFS)-type := stage +$(FSP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +ifneq ($(wildcard $($(FSP_CBFS)-file)),) + cbfs-files-y += $(FSP_CBFS) +endif diff --git a/src/soc/mediatek/mt8189/include/soc/memlayout.ld b/src/soc/mediatek/mt8189/include/soc/memlayout.ld index 66705329d2..7e77a816ed 100644 --- a/src/soc/mediatek/mt8189/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8189/include/soc/memlayout.ld @@ -65,6 +65,7 @@ SECTIONS DRAM_DMA(0x40000000, 1M) POSTRAM_CBFS_CACHE(0x40100000, 2M) RAMSTAGE(0x40300000, 2M) + FSP_RAMSTAGE_INIT_CODE(0x40500000, 2M) BL31(0x54600000, 0x60000) }