From 98ea8588be955abc69f8d6012623d3b39b062f62 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 13 Mar 2017 17:36:39 -0700 Subject: [PATCH] UPSTREAM: drivers/intel/fsp1_1: Only display MMCONF address if supported Disable the display of the MMCONF_BASE_ADDRESS if it is not supported. TEST=Build and run on Galileo Gen2 Change-Id: Ib5096ea1d53d56792b88bfb2d5c5ba0b22e9f89a Signed-off-by: Patrick Georgi Original-Commit-Id: c253a92299d832a39af4bed1818255ab61674d10 Original-Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea Original-Signed-off-by: Lee Leahy Original-Reviewed-on: https://review.coreboot.org/18801 Original-Reviewed-by: Paul Menzel Original-Tested-by: Martin Roth Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/455820 --- src/drivers/intel/fsp1_1/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 73fb66dee6..3933b2e193 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -60,8 +60,9 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) memset(&pei_data, 0, sizeof(pei_data)); /* Display parameters */ - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); + if (!IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); printk(BIOS_INFO, "Using FSP 1.1\n"); /* Display FSP banner */