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rockchip/rk3399: sdram: correct read obs and set DQS driver register error

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we use wrong register when read obs value and set DQS driver,
even not affect LPDDR3 performance now, but still need to correct it.

BUG=none
BRANCH=none
TEST=boot from kevin

Change-Id: Ie179f9a2955c5712951d40b3ada9c14a51c09c8d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/363170
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Lin Huang 2016-07-26 10:29:45 +08:00 • committed by chrome-bot
commit 98221e6b03
1 changed files with 3 additions and 3 deletions
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6
src/soc/rockchip/rk3399/sdram.c
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@ -424,7 +424,7 @@ static void phy_io_config(u32 channel,
/* PHY_926 PHY_PAD_DATA_DRIVE */
clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
/* PHY_927 PHY_PAD_DQS_DRIVE */
clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
/* PHY_928 PHY_PAD_ADDR_DRIVE */
clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
/* PHY_929 PHY_PAD_CLK_DRIVE */
@ -441,7 +441,7 @@ static void phy_io_config(u32 channel,
/* PHY_926 PHY_PAD_DATA_DRIVE */
clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9);
/* PHY_927 PHY_PAD_DQS_DRIVE */
clrsetbits_le32(&denali_phy[926], 0x3 << 9, mode_sel << 9);
clrsetbits_le32(&denali_phy[927], 0x3 << 9, mode_sel << 9);
/* PHY_928 PHY_PAD_ADDR_DRIVE */
clrsetbits_le32(&denali_phy[928], 0x3 << 17, mode_sel << 17);
/* PHY_929 PHY_PAD_CLK_DRIVE */
@ -720,7 +720,7 @@ static int data_training(u32 channel,
*/
obs_0 = read32(&denali_phy[532]);
obs_1 = read32(&denali_phy[660]);
obs_2 = read32(&denali_phy[789]);
obs_2 = read32(&denali_phy[788]);
if (((obs_0 >> 30) & 0x3) ||
((obs_1 >> 30) & 0x3) ||
((obs_2 >> 30) & 0x3))