From 980dff7eff87d9348bfffc33beef105ea5b47782 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 15 Dec 2000 00:58:14 +0000 Subject: [PATCH] Continuing fixes for acer. --- romimages/RON_ASUS_CUA/Makefile | 2 - romimages/RON_ASUS_CUA/ldscript.ld | 2 +- src/include/pci_ids.h | 3 + src/northbridge/acer/m1631/raminit.inc | 134 +++++++++++++++++++++++ src/southbridge/acer/m1535/southbridge.c | 38 +++++++ 5 files changed, 176 insertions(+), 3 deletions(-) diff --git a/romimages/RON_ASUS_CUA/Makefile b/romimages/RON_ASUS_CUA/Makefile index f546e54127..e6afa1aff3 100644 --- a/romimages/RON_ASUS_CUA/Makefile +++ b/romimages/RON_ASUS_CUA/Makefile @@ -5,12 +5,10 @@ CPUFLAGS += -DINTEL_PPRO_MTRR CPUFLAGS += -DNEWPCI CPUFLAGS += -DSERIAL_CONSOLE CPUFLAGS += -DFINAL_MAINBOARD_FIXUP -CPUFLAGS += -DPROTECTED_MODE_STARTUP # If you enable FIXED_AND_VARIABLE it never makes it to the kernel! # you have to only enable variable. CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS CPUFLAGS += -DRAMTEST -CPUFLAGS += -DUSE_DOC_MIL # This makes it fail sooner ... #CPUFLAGS += -DINBUF_COPY CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "' diff --git a/romimages/RON_ASUS_CUA/ldscript.ld b/romimages/RON_ASUS_CUA/ldscript.ld index 9c5739ca14..dc381796bf 100644 --- a/romimages/RON_ASUS_CUA/ldscript.ld +++ b/romimages/RON_ASUS_CUA/ldscript.ld @@ -37,7 +37,7 @@ _RAMBASE = 0x05000; _KERNSTK = 0x90000; /* should be parameterized but is not, yuck! */ -_ROMBASE = 0x80000; +_ROMBASE = 0xf0000; /* * Entry point is not really nececary, since the mkrom(8) diff --git a/src/include/pci_ids.h b/src/include/pci_ids.h index 8d3ae31ba4..4050a79ae8 100644 --- a/src/include/pci_ids.h +++ b/src/include/pci_ids.h @@ -859,6 +859,9 @@ #define PCI_DEVICE_ID_ATT_L56XMF 0x0440 #define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480 +#define PCI_VENDOR_ID_ACER 0x10b9 +#define PCI_DEVICE_ID_ACER_M1535D 0x1533 + #define PCI_VENDOR_ID_SPECIALIX 0x11cb #define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 #define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 diff --git a/src/northbridge/acer/m1631/raminit.inc b/src/northbridge/acer/m1631/raminit.inc index df30a36d8c..81f1b29453 100644 --- a/src/northbridge/acer/m1631/raminit.inc +++ b/src/northbridge/acer/m1631/raminit.inc @@ -1,3 +1,4 @@ +#if 0 /*** *** sungeun *** @@ -791,3 +792,136 @@ configure_next: /*** *** END REAL STUFF ****/ +#endif +#include +#include + +/* wow, the usual way to to this hurts. So we do it our way: + * 32-bit test not needed. + */ +/* the MCR is 32-bits. You set it, it programs SDRAM. + * first check: get Column address size (CAS) + * Start out assuming that it is 8 bits, then grow. + * nicely, if we put the 32-bit MCR value in %ecs, we can + * ror it 16 bits, and as we grow the CAS, we just inc cs, and that will + * set the right value. + */ +#define INIT_MCR $0xf6621000 +#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx +/*#include */ + +/* make the flash writeable */ +/* select the south bridge, register 44 (base) */ +/* south bridge is device 7. 7 << 3 is 0x38 */ + movl $0x80003844, %eax + mov $0x0cf8,%dx + outl %eax,%dx +/* but 0x40 makes flash writeable. You need this for DoC */ + movb $0x40, %al +/* 0xff selects register 0x47 */ + movb $0xff, %dl + outb %al,%dx + + xorl %edi, %edi + movl $0x8000006c, %eax + mov $0x0cf8,%dx + outl %eax,%dx +/* movb $0x8000006c, %al + CALLSP(pci_read_dword)*/ + movb $0xfc, %dl + inl %dx, %eax + movl %eax, %ecx + andl $0xfffc, %ecx + orl INIT_MCR, %ecx + WRITE_MCR0 + /* + movb $0x6c, %al + CALLSP(pci_write_dword) + */ + rorl $16, %ecx + /* clear out the CAS, since we assume start at zero + * and increment + */ + andb $0xf0, %cl + /* test 8 bit CAS */ + movb $0, 0 + movb $1, 0x800 + cmpb $0,0 + jnz sizeram + inc %cl + /* change the value we store each time. It makes debugging easier */ + movb $2, 0x1000 + cmpb $0, 0 + jnz sizeram + inc %cl + movb $3, 0x2000 + cmpb $0, 0 + jnz sizeram + inc %cl + +sizeram: + rorl $16, %ecx + /* clear the 'no multi page' bit. */ + andw $0xefff, %cx + WRITE_MCR0 + /* + mov $0x6c, %al + CALLSP(pci_write_dword) + */ +/* size is now in cx[19:16] */ +/* now size the dram */ +/* you had best have at least 4M; that's as small as we go */ +/* rorr 20 the ecx value, to get row size into lsb */ + movb $0, 0 + ror $20, %ecx + /* clear the size out to 4 MB */ + andb $0xf8, %cl + /* 4 MB */ + movl $0x400000, %esi +1: + + /* move a 4 to the next power-of-two address. + * if there is no memory there, it will wrap to zero + */ + movb $4, %es:(%esi) + + cmpb $0, 0 + /* if there is not a 0 at 0, the last write wrapped. Hop out */ + jne 1f + inc %cl + rol $1, %esi + jmp 1b +/* size is now in esi */ +/* %ecx has setting for register */ +1: + rol $20, %ecx +/* set 4 banks. */ + orb $1, %cl + WRITE_MCR0 + /* + mov $0x6c, %al + CALLSP(pci_write_dword) + */ +/* bank detect */ +/* you don't need to even care how large CAS is. + * Just set 4-bank mode, and set non-zero numbers into a few places. + * if the byte at 0 changes, you have two banks. Trivial. + */ + movb $0, 0 + movb $5, 0x1000 + movb $6, 0x2000 + movb $7, 0x4000 + cmpb $0, 0 + jz 1f /* only one bank */ + orl $0x80000, %ecx +1: + /* clear 4 banks */ + andb $0xfe, %cl + WRITE_MCR0 + movl $0x8000007c, %eax + movb $0xf8, %dl + outl %eax, %dx + movl $0x2423c411, %eax + movb $0xfc, %dl + outl %eax, %dx + diff --git a/src/southbridge/acer/m1535/southbridge.c b/src/southbridge/acer/m1535/southbridge.c index 85505d3522..6a526829a9 100644 --- a/src/southbridge/acer/m1535/southbridge.c +++ b/src/southbridge/acer/m1535/southbridge.c @@ -1,16 +1,54 @@ #include +#include #include #include void southbridge_fixup() { + struct pci_dev *pcidev; + + pcidev = pci_find_device(PCI_VENDOR_ID_ACER, + PCI_DEVICE_ID_ACER_M1535D, (void *)NULL); + if (!pcidev) { + printk(KERN_ERR __FUNCTION__ "no southbridge for 0x%x:0x%x\n", + PCI_VENDOR_ID_ACER, PCI_DEVICE_ID_ACER_M1535D); + return; + } + /* enable legacy decode */ + pci_write_config_dword(pcidev, 0x70, 0xffffffff); + + /* ENABLE SERIAL IRQ */ + pci_write_config_byte(pcidev, 0x70, 0x8); + + } void nvram_on() { + struct pci_dev *pcidev; + + pcidev = pci_find_device(PCI_VENDOR_ID_ACER, + PCI_DEVICE_ID_ACER_M1535D, (void *)NULL); + if (!pcidev) { + printk(KERN_ERR __FUNCTION__ "no southbridge for 0x%x:0x%x\n", + PCI_VENDOR_ID_ACER, PCI_DEVICE_ID_ACER_M1535D); + return; + } + /* turn on the rom at the high addresses, i.e. 0xfff80000 - 0xffffffff */ + /* also make it writeable */ + /* 0x47 is the register. the 0x47 value means: writeenable, enable addresses + * 0xfffc0000-0xfffdffff, 0xfffe0000-0xfffeffff, 0xffff0000-0xffffffff */ + pci_write_config_byte(pcidev, 0x47, 0x47); + pci_write_config_byte(pcidev, 0x70, 1); + + /* ENABLE 8 MBIT FLASH ROM FUNCTION */ + pci_write_config_byte(pcidev, 0x4E, 0x2); + } + void keyboard_on() { } +