From 97f9ebb5c24fda9de613ea51e6fe3784260e7704 Mon Sep 17 00:00:00 2001 From: Varun Upadhyay Date: Tue, 29 Jul 2025 09:01:53 +0530 Subject: [PATCH] mb/google/ocelot: Create ojal variant Create the ojal variant of the ocelot reference board by copying the ocelot files to a new directory named for the variant. BUG=b:437459757 TEST=1. Build emerge-ocelot 2. Run part_id_gen tool without any errors Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da Signed-off-by: Varun Upadhyay Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro Reviewed-by: Pranava Y N --- src/ec/google/chromeec/rtk.c | 6 +- src/mainboard/google/ocelot/Kconfig | 17 + src/mainboard/google/ocelot/Kconfig.name | 3 + src/mainboard/google/ocelot/bootblock.c | 8 + .../baseboard/ocelot/include/baseboard/ec.h | 3 +- .../baseboard/ocelot/include/baseboard/gpio.h | 2 +- .../google/ocelot/variants/ojal/Makefile.mk | 6 + .../google/ocelot/variants/ojal/gpio.c | 409 ++++++++++++++++++ .../google/ocelot/variants/ojal/hda_verb.c | 126 ++++++ .../ocelot/variants/ojal/include/variant/ec.h | 8 + .../variants/ojal/include/variant/gpio.h | 11 + .../google/ocelot/variants/ojal/memory.c | 59 +++ .../ocelot/variants/ojal/memory/Makefile.mk | 7 + .../ojal/memory/dram_id.generated.txt | 7 + .../variants/ojal/memory/mem_parts_used.txt | 12 + .../ocelot/variants/ojal/overridetree.cb | 5 + 16 files changed, 685 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/google/ocelot/variants/ojal/Makefile.mk create mode 100644 src/mainboard/google/ocelot/variants/ojal/gpio.c create mode 100644 src/mainboard/google/ocelot/variants/ojal/hda_verb.c create mode 100644 src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h create mode 100644 src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory.c create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/ocelot/variants/ojal/overridetree.cb diff --git a/src/ec/google/chromeec/rtk.c b/src/ec/google/chromeec/rtk.c index 96ffbe5364..bd2f87d0ed 100644 --- a/src/ec/google/chromeec/rtk.c +++ b/src/ec/google/chromeec/rtk.c @@ -71,7 +71,8 @@ bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum) printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %zu\n", port, length); if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) { - uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START)); + uint8_t *p = (uint8_t *)(uintptr_t)(HOSTCMD_PARAM_MEM_BASE + + (port - EMI_RANGE_START)); for (i = 0; i < length; ++i) { dest[i] = p[i]; if (csum) @@ -91,7 +92,8 @@ bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum) printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %zu\n", port, length); if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) { - uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START)); + uint8_t *p = (uint8_t *)(uintptr_t)(HOSTCMD_PARAM_MEM_BASE + + (port - EMI_RANGE_START)); for (i = 0; i < length; ++i) { p[i] = msg[i]; if (csum) diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig index bfcb9af577..131948e44a 100644 --- a/src/mainboard/google/ocelot/Kconfig +++ b/src/mainboard/google/ocelot/Kconfig @@ -64,6 +64,16 @@ config BOARD_GOOGLE_MODEL_OCELOT select DRIVERS_INTEL_TOUCH select FSP_UGOP_EARLY_SIGN_OF_LIFE +config BOARD_GOOGLE_MODEL_OJAL + def_bool n + select BOARD_GOOGLE_BASEBOARD_OCELOT + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_INTEL_TOUCH + select FSP_UGOP_EARLY_SIGN_OF_LIFE + select EC_GOOGLE_CHROMEEC_RTK + select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE + config BOARD_GOOGLE_OCELOT select BOARD_GOOGLE_MODEL_OCELOT @@ -84,6 +94,9 @@ config BOARD_GOOGLE_OCELOTMCHP4ES select BOARD_GOOGLE_MODEL_OCELOT select EC_GOOGLE_CHROMEEC_MEC +config BOARD_GOOGLE_OJAL + select BOARD_GOOGLE_MODEL_OJAL + if BOARD_GOOGLE_OCELOT_COMMON config BASEBOARD_DIR @@ -118,6 +131,7 @@ config DRIVER_TPM_I2C_ADDR config DRIVER_TPM_I2C_BUS hex default 0x01 if BOARD_GOOGLE_MODEL_OCELOT + default 0x01 if BOARD_GOOGLE_MODEL_OJAL config HAVE_SLP_S0_GATE def_bool n @@ -131,6 +145,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT + default "Ojal" if BOARD_GOOGLE_OJAL config MEMORY_SOLDERDOWN def_bool n @@ -140,6 +155,7 @@ config MEMORY_SOLDERDOWN config TPM_TIS_ACPI_INTERRUPT int default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17) + default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17) config UART_FOR_CONSOLE int @@ -151,6 +167,7 @@ config USE_PM_ACPI_TIMER config VARIANT_DIR string default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT + default "ojal" if BOARD_GOOGLE_MODEL_OJAL config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/ocelot/Kconfig.name b/src/mainboard/google/ocelot/Kconfig.name index 71a69cb31a..2645d9c7f0 100644 --- a/src/mainboard/google/ocelot/Kconfig.name +++ b/src/mainboard/google/ocelot/Kconfig.name @@ -11,6 +11,9 @@ config BOARD_GOOGLE_OCELOTITE config BOARD_GOOGLE_OCELOTMCHP bool "-> Ocelotmchp" +config BOARD_GOOGLE_OJAL + bool "-> Ojal" + config BOARD_GOOGLE_OCELOT4ES bool "-> Ocelot4ES" diff --git a/src/mainboard/google/ocelot/bootblock.c b/src/mainboard/google/ocelot/bootblock.c index 6ee655ee58..e414937b83 100644 --- a/src/mainboard/google/ocelot/bootblock.c +++ b/src/mainboard/google/ocelot/bootblock.c @@ -2,6 +2,7 @@ #include #include +#include void bootblock_mainboard_early_init(void) { @@ -11,3 +12,10 @@ void bootblock_mainboard_early_init(void) pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); } + +void bootblock_mainboard_init(void) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)) + lpc_open_mmio_window(CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_BASE, + CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_SIZE); +} diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h index 1302946b93..aa8f052b47 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/ec.h @@ -75,7 +75,8 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -#if !CONFIG(BOARD_GOOGLE_OCELOT) && !CONFIG(BOARD_GOOGLE_OCELOT4ES) +#if !CONFIG(BOARD_GOOGLE_OCELOT) && !CONFIG(BOARD_GOOGLE_OCELOT4ES) && \ +!CONFIG(BOARD_GOOGLE_OJAL) #define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ #endif diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h index cf5924634d..e72f1ba74d 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h @@ -13,7 +13,7 @@ * GPIO_PCH_WP - WP signal to PCH */ //TODO for Nuvo: #define EC_SYNC_IRQ GPP_E07_IRQ -#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) +#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL) #define EC_SYNC_IRQ 0 /* Not Connected */ #endif #define GPIO_PCH_WP GPP_D02 diff --git a/src/mainboard/google/ocelot/variants/ojal/Makefile.mk b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk new file mode 100644 index 0000000000..4c33dad4db --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/ocelot/variants/ojal/gpio.c b/src/mainboard/google/ocelot/variants/ojal/gpio.c new file mode 100644 index 0000000000..dcef9f7579 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/gpio.c @@ -0,0 +1,409 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* GPP_A */ + /* GPP_A00: ESPI_IO0_AIC */ + /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ + + /* GPP_A01: ESPI_IO1_AIC */ + /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */ + + /* GPP_A02: ESPI_IO2_AIC */ + /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */ + + /* GPP_A03: ESPI_IO3_AIC */ + /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */ + + /* GPP_A04: ESPI_CS0_AIC_N */ + /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */ + + /* GPP_A05: ESPI_CLK_AIC */ + /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */ + + /* GPP_A06: ESPI_RST_AIC_N */ + /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ + + /* GPP_A08: M2_GEN4_SSD_RESET_N */ + PAD_CFG_GPO(GPP_A08, 1, PLTRST), + /* GPP_A09: M.2_WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), + /* GPP_A10: WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_A10, 1, PLTRST), + /* GPP_A11: WLAN_RST_N */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_A12: WIFI_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), + /* GPP_A13: PCIE_LNK_DOWN */ + PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI), + /* GPP_A15: CODEC_GPIO_EN */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), + + /* GPP_B */ + /* GPP_B00: USBC_SML_CLK_PD */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), + /* GPP_B01: USBC_SML_DATA_PD */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), + /* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */ + PAD_NC(GPP_B03, NONE), + /* GPP_B04: ISH_GP_0_SNSR_HDR */ + PAD_NC(GPP_B04, NONE), + /* GPP_B06: SOC_PDB_CTRL */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), + /* GPP_B08: ISH_GP_4_SNSR_HDR */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_B09, 1, DEEP), + /* GPP_B10: NC */ + PAD_NC(GPP_B10, NONE), + /* GPP_B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: GPP_B14_DDSP_HPDB */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), + /* GPP_B16: COINLESS_MODE_SELECT */ + PAD_CFG_GPI(GPP_B16, NONE, DEEP), + /* GPP_B17: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_B20: WWAN_RST_N */ + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + /* GPP_B21: TCP_RETIMER_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* GPP_B24: ESPI_ALERT0_EC_R_N */ + PAD_NC(GPP_B24, NONE), + /* GPP_B25: None */ + PAD_NC(GPP_B25, NONE), + + /* GPP_C */ + /* GPP_C00: SPD_SMB_CLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: SPD_SMB_DATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C02: NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03: TCP_LAN_SML0_SCL_R */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04: TCP_LAN_SML0_SDA_R */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C05: NC */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06: NC */ + PAD_NC(GPP_C06, NONE), + /* GPP_C07: NC */ + PAD_NC(GPP_C07, NONE), + /* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */ + PAD_CFG_GPO(GPP_C08, 1, PLTRST), + /* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */ + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), + /* GPP_C10: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), + /* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C22: DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), + /* GPP_C23: DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), + + /* GPP_D */ + /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D02: SOC_WP_OD */ + PAD_CFG_GPO(GPP_D02, 0, DEEP), + /* GPP_D03: X4_SLOT_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL), + /* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */ + PAD_NC(GPP_D07, NONE), + /* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09: I2S_MCLK_HDR */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1), + /* GPP_D10: HDA_BCLK (HDR) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11: HDA_SYNC (HDR) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + /* GPP_D12: HDA_SDO (HDR) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* GPP_D13: HDA_SDI0 (HDR) */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D16: HDA_RST_N (HDR) */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + /* GPP_D17: HDA_SDI1 (HDR) */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D19: NC */ + PAD_NC(GPP_D19, NONE), + /* GPP_D21: GPP_D21_UFS_REFCLK_R */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + + /* GPP_E */ + /* GPP_E01: PM_SLP_DRAM_N */ + PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2), + /* GPP_E02: NC */ + PAD_NC(GPP_E02, NONE), + /* GPP_E03: X4_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E05: GPP_E5_FPS_PWREN */ + PAD_CFG_GPO(GPP_E05, 1, DEEP), + /* GPP_E06: GPP_E6_PEN_DETECT */ + PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI), + /* GPP_E07: LAN_GPIO_RST_N */ + PAD_CFG_GPO(GPP_E07, 1, PLTRST), + /* GPP_E08: EC_SOC_INT_ODL */ + PAD_CFG_GPI(GPP_E08, NONE, DEEP), + /* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */ + PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), + /* GPP_E10: M2_UFS_DET_SEL_N */ + PAD_CFG_GPI(GPP_E10, NONE, DEEP), + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + /* GPP_E17: GPP_E17_GSPI0A_CS0 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_E19: FPS_INT_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT), + /* GPP_E20: FPS_FW_UPDATE */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E22: NC */ + PAD_NC(GPP_E22, NONE), + + /* GPP_F */ + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06: DISC_WLAN_WWAN_COEX3 */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), + /* GPP_F07: FUSA_DIAGTEST_EN_HDR */ + PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), + /* GPP_F08: TCH_PNL1_PWR_EN */ + PAD_CFG_GPO(GPP_F08, 1, PLTRST), + /* GPP_F09: M2_UFS_RST_N */ + PAD_CFG_GPO(GPP_F09, 1, DEEP), + /* GPP_F10: X4_PCIE_SLOT1_PWR_EN */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11), + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), + /* GPP_F14: GPP_F14_GPSI0A_MOSI */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), + /* GPP_F15: GPP_F15_GSPI0A_MISO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), + /* GPP_F16: GPP_F16_GSPI0A_CLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F17: CODEC_IRQ_HDR */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* GPP_F18: TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_F19: NC */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20: CSE_EARLY_SW */ + PAD_CFG_GPI(GPP_F20, NONE, DEEP), + /* GPP_F22: THC1_SPI2_DSYNC */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), + + /* GPP_H */ + /* GPP_H00: NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01: M2_UFS_SLP_N */ + PAD_CFG_GPO(GPP_H01, 1, DEEP), + /* GPP_H02: DEBUG_TRACE_PNP */ + PAD_CFG_GPO(GPP_H02, 1, PLTRST), + /* GPP_H03: MIC MUTE */ + PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), + /* GPP_H04: CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), + /* GPP_H05: CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), + /* GPP_H06: I2C3_SCL_AUDIO_HDR */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SDA_AUDIO_HDR */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10: UART0_BUF_RTS */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* GPP_H11: UART0_BUF_CTS */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* GPP_H13: CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */ + PAD_NC(GPP_H14, NONE), + /* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */ + PAD_NC(GPP_H15, NONE), + /* GPP_H17: MIC MUTE LED */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_H18, 1, DEEP), + /* GPP_H19: I3C0_SDA_HDR */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), + /* GPP_H20: I3C0_SCL_HDR */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), + /* GPP_H21: I2C1_SDA_TTK_CHROME */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: I2C1_SCL_TTK_CHROME */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_H23: TP */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + /* GPP_H24: TP */ + PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1), + + /* GPP_S */ + /* GPP_S00: SNDW3_CLK_CODEC (HDR) */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SNDW3_DATA0_CODEC (HDR) */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SNDW3_DATA1_CODEC (HDR) */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* GPP_S03: SNDW3_DATA2_CODEC (HDR) */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* GPP_S04: DMIC0_CLK (HDR) */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5), + /* GPP_S05: DMIC0_DATA (HDR) */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5), + /* GPP_S06: DMIC1_CLK (HDR) */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5), + /* GPP_S07: DMIC1_DATA (HDR) */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5), + + /* GPP_V */ + /* GPP_V00: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01: BC_ACOK_MCP */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02: LANWAKE_N_R */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: PWRBTN_MCP_N */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04: PM_SLP_S3_N */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05: PM_SLP_S4_N */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06: PM_SLP_A_N */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */ + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), + /* GPP_V08: SLP_WLAN_N */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09: PM_SLP_S5_N */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10: LANPHYPC_R_N */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11: PM_SLP_LAN_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12: WAKE_N */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: GPP_V14_FORCEPR_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: GPP_V16_VCCST_EN */ + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_B17: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT), + /* GPP_H06: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H21: I2C1_SDA_TTK_CHROME */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: I2C1_SCL_TTK_CHROME */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), +}; + +/* Pad configuration in romstage */ +static const struct pad_config romstage_gpio_table[] = { + /* GPP_C00: SPD_SMB_CLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: SPD_SMB_DATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO(GPP_C15, 0, PLTRST), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/ocelot/variants/ojal/hda_verb.c b/src/mainboard/google/ocelot/variants/ojal/hda_verb.c new file mode 100644 index 0000000000..2f703b78ee --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/hda_verb.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ + 0x10ec12ac, /* Subsystem ID */ + 0x00000013, /* Number of jacks (NID entries) */ + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting-1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h b/src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h new file mode 100644 index 0000000000..4fc0622f15 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h b/src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h new file mode 100644 index 0000000000..cced66807a --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/ocelot/variants/ojal/memory.c b/src/mainboard/google/ocelot/variants/ojal/memory.c new file mode 100644 index 0000000000..1315639496 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/memory.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#define SMBUS_ADDR_DIMM 0x50 + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 10, 11, 8, 9, 15, 14, 12, 13, }, + .dq1 = { 7, 4, 5, 6, 3, 0, 2, 1 }, + }, + .ddr1 = { + .dq0 = { 8, 11, 10, 9, 15, 12, 13, 14, }, + .dq1 = { 6, 7, 5, 4, 1, 3, 0, 2 }, + }, + .ddr2 = { + .dq0 = { 3, 2, 1, 0, 6, 7, 5, 4, }, + .dq1 = { 9, 8, 10, 11, 15, 12, 13, 14 }, + }, + .ddr3 = { + .dq0 = { 8, 11, 10, 9, 15, 13, 12, 14, }, + .dq1 = { 4, 5, 6, 7, 1, 3, 2, 0 }, + }, + }, + + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + }, + + .ect = true, /* Early Command Training */ + + .lp_ddr_dq_dqs_re_training = 1, + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp5x_config = { + .ccc_config = 0xFF, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &lp5_mem_config; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = 0; +} diff --git a/src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk b/src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk new file mode 100644 index 0000000000..aa231270d4 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/memory/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ojal/memory src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 0(0b0000) Parts = H58G66BK8BX067 diff --git a/src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt b/src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt new file mode 100644 index 0000000000..593ce55be7 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/ocelot/variants/ojal/memory src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H58G66BK8BX067 0 (0000) diff --git a/src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt b/src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt new file mode 100644 index 0000000000..821d48ec13 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/memory/mem_parts_used.txt @@ -0,0 +1,12 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +H58G66BK8BX067 diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb new file mode 100644 index 0000000000..47cdd94f4b --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/pantherlake + + device domain 0 on + end +end