From 97d9c985ce6b30b25edbabe641b2665ab2fd560d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 23 Jan 2026 11:22:07 -0600 Subject: [PATCH] soc/intel/{mtl,ptl}/fsp_params: Program PcieRpDetectTimeoutMs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This UPD is programmed for ADL, but not MTL and PTL. Add it to the latter two so it functions as expected when set in devicetree for a given PCIe root port. TEST=build/boot Starlabs Starfighter MTL, verify Samsung NVMe drive reliably detected in PCH-attached socket when timeout increased. Change-Id: Iea744fed987d413c6487559005d668329a05fff4 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/90877 Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes Reviewed-by: Subrata Banik Reviewed-by: Jérémy Compostella --- src/soc/intel/meteorlake/fsp_params.c | 1 + src/soc/intel/pantherlake/fsp_params.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 61be03ad47..5e7bdc53ab 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -641,6 +641,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; configure_pch_rp_power_management(s_cfg, rp_cfg, i); } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 0133e72c00..2fbcbea5b9 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -639,6 +639,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; if (rp_cfg->pcie_rp_aspm) s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); }