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Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode

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Depending on the init_fb parameter:
1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this
same page
2) For developer/recovery mode, we init the gtt to consecutive pages

BUG=None
BRANCH=None
TEST=Built and booted on falco with normal, developer and recovery mode. Graphics
initialization worked fine.

Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Furquan Shaikh 2013-08-12 15:48:19 -07:00 • committed by ChromeBot
commit 97c99dfe52
2 changed files with 29 additions and 8 deletions
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21
src/mainboard/google/slippy/gma.c
View file

@ -43,6 +43,7 @@
#include <cpu/x86/msr.h>
#include <edid.h>
#include <drivers/intel/gma/i915.h>
/*
* Here is the rough outline of how we bring up the display:
* 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
@ -271,10 +272,9 @@ void mainboard_train_link(struct intel_dp *intel_dp)
}
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
unsigned int gfx);
unsigned int gfx, unsigned int init_fb);
int i915lightup(unsigned int pphysbase, unsigned int piobase,
unsigned int pmmio, unsigned int pgfx)
unsigned int pmmio, unsigned int pgfx, unsigned int init_fb)
{
int must_cycle_power = 0;
struct intel_dp adp, *dp = &adp;
@ -297,6 +297,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
void runio(struct intel_dp *dp);
void runlinux(struct intel_dp *dp);
dp->gen = 8; // ??
dp->is_haswell = 1;
dp->DP = 0x2;
@ -316,6 +317,17 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
dp->aux_clock_divider = 0xe1;
dp->precharge = 3;
/* 1. Normal mode: Set the first page to zero and make
all GTT entries point to the same page
2. Developer/Recovery mode: We do not zero out all
the pages pointed to by GTT in order to avoid wasting time */
if (init_fb)
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
else {
setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
memset((void*)graphics, 0, 4096);
}
//intel_prepare_ddi_buffers(0, 0);
//ironlake_edp_panel_vdd_on(dp);
dp->address = 0x50;
@ -345,9 +357,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
io_i915_write32(0x00000021,0x6f410);
runio(dp);
palette();
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
palette();
pixels = dp->edid.ha * (dp->edid.va-4) * 4;
printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);

16
src/northbridge/intel/haswell/gma.c
View file

@ -29,6 +29,10 @@
#include "chip.h"
#include "haswell.h"
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
struct gt_reg {
u32 reg;
u32 andmask;
@ -402,12 +406,18 @@ static void gma_func0_init(struct device *dev)
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
u32 iobase, mmiobase, physbase;
/* Default set to 1 since it might be required for
stuff like seabios */
unsigned int init_fb = 1;
iobase = dev->resource_list[2].base;
mmiobase = dev->resource_list[0].base;
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base);
#ifdef CONFIG_CHROMEOS
init_fb = developer_mode_enabled() || recovery_mode_enabled();
#endif
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
unsigned int gfx, unsigned int init_fb);
lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base, init_fb);
#endif
if (! lightup_ok) {
printk(BIOS_SPEW, "FUI did not run; using VBIOS\n");