From 97bc829c53536d6dd9b60b13154f22035caf2a26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 13 Jun 2017 14:05:09 +0200 Subject: [PATCH] UPSTREAM: soc/intel/apollolake: Removing some menuconfig options Does not need to changeable in menuconfig. BUG=none BRANCH=none TEST=none Change-Id: I0bef7f608ed615d4c32dfbe475d424ad3680341c Signed-off-by: Patrick Georgi Original-Commit-Id: 3038b48de36d69c26c29977d1ff8afc7953febf3 Original-Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4 Original-Signed-off-by: Arthur Heymans Original-Reviewed-on: https://review.coreboot.org/20177 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Sumeet R Pawnikar Reviewed-on: https://chromium-review.googlesource.com/539213 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/soc/intel/apollolake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b80941d0dd..deb510eda3 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -113,11 +113,11 @@ config PCR_BASE_ADDRESS This option allows you to select MMIO Base Address of sideband bus. config DCACHE_RAM_BASE - hex "Base address of cache-as-RAM" + hex default 0xfef00000 config DCACHE_RAM_SIZE - hex "Length in bytes of cache-as-RAM" + hex default 0xc0000 help The size of the cache-as-ram region required during bootblock @@ -140,7 +140,7 @@ config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL - hex "MMIO base address for UART" + hex default 0xde000000 config SOC_UART_DEBUG