diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig
index ea3c7d2ece..786236478c 100644
--- a/src/soc/mediatek/mt8189/Kconfig
+++ b/src/soc/mediatek/mt8189/Kconfig
@@ -16,6 +16,7 @@ config SOC_MEDIATEK_MT8189
 	select SOC_MEDIATEK_COMMON
 	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
+	select MEDIATEK_DSI_CPHY
 
 if SOC_MEDIATEK_MT8189
 
diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk
index 02e2847123..351c94190b 100644
--- a/src/soc/mediatek/mt8189/Makefile.mk
+++ b/src/soc/mediatek/mt8189/Makefile.mk
@@ -46,6 +46,7 @@ ramstage-y += ../common/dp/dp_intf_v2.c
 ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_v2.c dptx.c
 ramstage-y += ../common/dp/dptx_hal_common.c ../common/dp/dptx_hal_v2.c  dptx_hal.c
 ramstage-y += ../common/dramc_info.c
+ramstage-y += ../common/dsi_common.c ../common/dsi_v1.c
 ramstage-y += ../common/emi.c
 ramstage-y += ../common/mcu.c mcupm.c
 ramstage-y += ../common/memory.c
@@ -55,6 +56,7 @@ ramstage-y += ../common/mt6315.c mt6315.c
 ramstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/mtk_fsp.c
+ramstage-y += ../common/mtk_mipi_cphy.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/pi_image.c
 ramstage-y += ../common/pmif.c ../common/pmif_clk.c ../common/pmif_init.c pmif_clk.c
 ramstage-y += ../common/pmif_spi.c pmif_spi.c
diff --git a/src/soc/mediatek/mt8189/include/soc/dsi.h b/src/soc/mediatek/mt8189/include/soc/dsi.h
index 443e743b87..ad3a04d721 100644
--- a/src/soc/mediatek/mt8189/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8189/include/soc/dsi.h
@@ -4,5 +4,59 @@
 #define SOC_MEDIATEK_MT8189_DSI_H
 
 #include <soc/dsi_common.h>
+#include <soc/dsi_register_v2.h>
+#include <types.h>
+
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 125
+#define MTK_DSI_HAVE_SIZE_CON 1
+#define PIXEL_STREAM_CUSTOM_HEADER 0xb
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0[3];
+	u32 lane_con;
+	u32 voltage_sel;
+	u32 reserved1[5];
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 phy_sel[4];
+	u32 reserved2[61];
+	u32 d2_sw_ctl_en;
+	u32 reserved3[63];
+	u32 d0_sw_ctl_en;
+	u32 reserved4[56];
+	u32 ck_ckmode_en;
+	u32 reserved5[6];
+	u32 ck_sw_ctl_en;
+	u32 reserved6[63];
+	u32 d1_sw_ctl_en;
+	u32 reserved7[63];
+	u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, voltage_sel, 0x10);
+check_member(mipi_tx_regs, pll_con4, 0x3C);
+check_member(mipi_tx_regs, phy_sel[0], 0x40);
+check_member(mipi_tx_regs, phy_sel[3], 0x4C);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX0_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
 
 #endif