From 970201012365bad68b1a6d71fcbc10f44694007d Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 16 Dec 2025 08:56:38 -0800 Subject: [PATCH] mb/google/fatcat: Fix Gen4 SSD power sequencing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move Gen4 SSD power enable (GPP_B10) from ramstage GPIO table to pre-memory configuration to ensure proper delay between power enable and reset signals. This is required to fix PCIe speed downgrade or link failure issues seen with some NVMe parts when a non-serial image is used for boot. Changes: - Enable GPP_B10 (GEN4_SSD_PWREN) in pre_mem_gen4_ssd_pwr_pads - Remove duplicate GPP_B10 configuration from gen4_ssd_pads - Remove GPP_B10 from ramstage gpio_table BUG=None TEST=Boot to OS, check PCIe link speed for SSD. Change-Id: I969a0d5576b9a229f70a4d01737b7f594876b106 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/90523 Reviewed-by: Huang, Cliff Reviewed-by: Subrata Banik Reviewed-by: Pranava Y N Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- .../google/fatcat/variants/fatcat/fw_config.c | 15 +++++++++++---- .../google/fatcat/variants/fatcat/gpio.c | 2 -- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index e0a59219a4..0344103453 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -235,14 +235,17 @@ static const struct pad_config wwan_disable_pads[] = { }; /* Gen4 NVME: at the top M.2 slot */ -static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = { +static const struct pad_config pre_mem_gen4_ssd_pwr_seq1_pads[] = { /* GPP_B10: GEN4_SSD_PWREN */ PAD_CFG_GPO(GPP_B10, 0, PLTRST), }; -static const struct pad_config gen4_ssd_pads[] = { +static const struct pad_config pre_mem_gen4_ssd_pwr_seq2_pads[] = { /* GPP_B10: GEN4_SSD_PWREN */ PAD_CFG_GPO(GPP_B10, 1, PLTRST), +}; + +static const struct pad_config gen4_ssd_pads[] = { /* GPP_B09: M2_GEN4_SSD_RESET_N */ PAD_CFG_GPO(GPP_B09, 1, PLTRST), }; @@ -568,11 +571,11 @@ void fw_config_configure_pre_mem_gpio(void) GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { - GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { - GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq1_pads); GPIO_CONFIGURE_PADS(pre_mem_gen5_ssd_pwr_pads); } @@ -592,6 +595,10 @@ void fw_config_configure_pre_mem_gpio(void) if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads); + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4)) || + fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_seq2_pads); + } } void fw_config_gpio_padbased_override(struct pad_config *padbased_table) diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index eb03641251..59dbe23680 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -55,8 +55,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3), /* GPP_B09: M2_GEN4_SSD_RESET_N */ PAD_CFG_GPO(GPP_B09, 1, PLTRST), - /* GPP_B10: GEN4_SSD_PWREN */ - PAD_CFG_GPO(GPP_B10, 1, PLTRST), /* GPP_B11: MOD_TCSS1_DISP_HPD3 */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), /* GPP_B12: PM_SLP_S0_N */