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aarch64: Enable early icache and migrate SCTLR from EL3

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Initial SCTLR setup done in arm_init_caches for EL3 is now
copied when switching to EL2.

BUG=None
BRANCH=none
TEST=Run coreboot and check for correct SCTLR_EL2 value

Change-Id: I88942ae913cb80c5ca561e5bdd790732dc3348d7
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187468
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Marcelo Povoa 2014-02-19 11:44:37 -08:00 • committed by chrome-internal-fetch
commit 96e7f0e603
2 changed files with 5 additions and 3 deletions
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1
src/arch/aarch64/bootblock_simple.c
View file

@ -45,7 +45,6 @@ void main(void)
/* Globally disable MMU, caches, and branch prediction (these should
* be disabled by default on reset) */
dcache_mmu_disable();
write_sctlr(read_sctlr() & ~(SCTLR_A));
/*
* Re-enable icache and branch prediction. MMU and dcache will be

7
src/arch/aarch64/cpu.S
View file

@ -90,13 +90,14 @@ ENTRY(arm_init_caches)
mrs x4, sctlr_el3
/* FIXME: How to enable branch prediction on ARMv8? */
msr sctlr_el3, x4
/* Flush and invalidate dcache */
bl flush_dcache_all
/* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
and x4, x4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
/* Activate ICache (12) already for speed */
orr x4, x4, #(1 << 12)
msr sctlr_el3, x4
/* Invalidate icache and TLB for good measure */
@ -108,7 +109,7 @@ ENTRY(arm_init_caches)
ret x8
ENDPROC(arm_init_caches)
/* From u-boot transition.S */
/* Based on u-boot transition.S */
ENTRY(switch_el3_to_el2)
mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */
msr scr_el3, x0
@ -121,6 +122,8 @@ ENTRY(switch_el3_to_el2)
msr sp_el2, x0 /* Migrate SP */
mrs x0, vbar_el3
msr vbar_el2, x0 /* Migrate VBAR */
mrs x0, sctlr_el3
msr sctlr_el2, x0 /* Migrate SCTLR */
mov x0, #0x3c9
msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */
msr elr_el3, x30