Drop the obsolete files reset.S, cache_as_ram.S and init.S.
Their contents are in arch/x86/stage0_i586.S now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@305 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
c34521a1d6
commit
96bc8ff02e
3 changed files with 0 additions and 449 deletions
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@ -1,259 +0,0 @@
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/* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Yinghai Lu, Tyan Corp.
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* Copyright (C) 2007 Stefan Reinauer, coresystems GmbH
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/* We will use 4Kbytes only for cache as ram. This is
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* enough to fit in our stack.
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*
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* disable HyperThreading is done by eswar
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* the other is very similar to the AMD CAR, except remove amd specific msr
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*/
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#define CacheSize 4096
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#define CacheBase (0xd0000 - CacheSize)
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#define ASSEMBLY
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#include "mtrr.h"
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/* Save the BIST result */
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movl %eax, %ebp
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CacheAsRam:
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/* Check whether the processor has HT capability */
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc NotHtProcessor
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bswapl %ebx
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cmpb $01, %bh
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jbe NotHtProcessor
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/* It is a HT processor; Send SIPI to the other logical processor
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* within this processor so that the CAR related common system
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* registers are programmed accordingly
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*/
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/* Use some register that is common to both logical processors
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* as semaphore. Refer Appendix B, Vol.3
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*/
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xorl %eax, %eax
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xorl %edx, %edx
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movl $0x250, %ecx
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wrmsr
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/* Figure out the logical AP's APIC ID; the following logic will work
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* only for processors with 2 threads.
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*
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* Refer to Vol 3. Table 7-1 for details about this logic
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*/
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movl $0xFEE00020, %esi
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movl (%esi), %ebx
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andl $0xFF000000, %ebx
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bswapl %ebx
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btl $0, %ebx
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jnc LogicalAP0
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andb $0xFE, %bl
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jmp SendSIPI
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LogicalAP0:
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orb $0x01, %bl
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SendSIPI:
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bswapl %ebx /* ebx - logical AP's APIC ID */
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/* Fill up the IPI command registers in the Local APIC mapped to
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* default address and issue SIPI to the other logical processor
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* within this processor die.
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*/
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RetrySIPI:
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movl %ebx, %eax
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movl $0xFEE00310, %esi
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movl %eax, (%esi)
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/* SIPI vector - F900:0000 */
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movl $0x000006F9, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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movl $0x30, %ecx
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SIPIDelay:
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pause
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decl %ecx
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jnz SIPIDelay
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movl (%esi), %eax
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andl $0x00001000, %eax
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jnz RetrySIPI
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/* Wait for the Logical AP to complete initialization */
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LogicalAPSIPINotdone:
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movl $0x250, %ecx
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rdmsr
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orl %eax, %eax
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jz LogicalAPSIPINotdone
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NotHtProcessor:
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/*Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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movl $0x269, %ecx
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wrmsr
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#endif
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#if CacheSize == 0x8000
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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#endif
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/* enable caching for 16K/8K/4K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_cc000*/
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#if CacheSize == 0x4000
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movl $0x06060606, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x2000
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movl $0x06060000, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x1000
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movl $0x06000000, %edx /* WB IO type */
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#endif
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xorl %eax, %eax
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wrmsr
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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/* Read the range with lodsl*/
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movl $CacheBase, %esi
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cld
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movl $(CacheSize>>2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize>>2), %ecx
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xorl %eax, %eax
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rep stosl
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#if 0
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/* check the cache as ram */
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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.xin1:
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movl %esi, %eax
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movl %eax, (%esi)
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decl %ecx
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je .xout1
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add $4, %esi
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jmp .xin1
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.xout1:
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movl $CacheBase, %esi
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// movl $(CacheSize>>2), %ecx
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movl $4, %ecx
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.xin1x:
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movl %esi, %eax
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movl $0x4000, %edx
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movb %ah, %al
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.testx1:
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outb %al, $0x80
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decl %edx
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jnz .testx1
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movl (%esi), %eax
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cmpb 0xff, %al
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je .xin2 /* dont show */
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movl $0x4000, %edx
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.testx2:
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outb %al, $0x80
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decl %edx
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jnz .testx2
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.xin2: decl %ecx
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je .xout1x
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add $4, %esi
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jmp .xin1x
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.xout1x:
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#endif
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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movw $CACHE_RAM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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lout:
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call stage1_main
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/* We will not go back */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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148
arch/x86/init.S
148
arch/x86/init.S
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@ -1,148 +0,0 @@
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# init code - switch cpu to pmode and enable cache as ram.
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#
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# Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL
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# Copyright (C) 2007 Stefan Reinauer, coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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#
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#include "macros.h"
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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.code16
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.globl _start
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_start:
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cli
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/* save the BIST result */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.tw.com for this TBL fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB */
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/* switch to protected mode */
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movw %cs, %ax
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shlw $4, %ax
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movw $gdt16 + 0xe000, %bx
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subw %ax, %bx
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data32 lgdt %cs:(%bx)
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST result */
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movl %ebp, %eax
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// port80_post (0x23) /* post 0x01 */
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/* Now we are in protected mode. Jump to a 32 bit code segment. */
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//data32 ljmp $ROM_CODE_SEG, $__protected_start
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data32 ljmp $ROM_CODE_SEG, $0xe058
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.align 4
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.globl gdt16
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gdt16 = . - _start
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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/* From now on we are 32bit */
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.code32
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/* This is the gdt for ROMCC/ASM part of LinuxBIOS. It
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* is different from the gdt in GCC part of LinuxBIOS.
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*
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* That on was defined in c_start.S in LinuxBIOS v2. TODO
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*/
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.align 4
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.globl gdtptr
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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#if 0
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//This code was used by v2. TODO
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.globl protected_start
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protected_start:
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_start
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#endif
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.globl __protected_start
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__protected_start:
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/* Save the BIST value */
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movl %eax, %ebp
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port80_post (0x01) /* post 0x01 */
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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#define CONFIG_CPUTYPE_INTEL 1
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#ifdef CONFIG_CPUTYPE_INTEL
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#include "cache_as_ram.S"
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#endif
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.align 4
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@ -1,42 +0,0 @@
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Stefan Reinauer <stepan@coresystems.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
|
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# Reset vector.
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# RVECTOR: size of reset vector, default is 0x10
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# RESRVED: size of vpd code, default is 0xf0
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# BOOTBLK: size of bootblock code, default is 0x1f00 (8k-256b)
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SEGMENT_SIZE = 0x10000
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RVECTOR = 0x00010
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.code16
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.globl _start
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_start:
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jmp SEGMENT_SIZE-(BOOTBLK+RESRVED+RVECTOR)
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.byte 0
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# Date? ID string? We might want to put something else in here.
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.ascii DATE
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# Checksum.
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.word 0
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