Added support for 64-bit base address registers.
This commit is contained in:
Ronald G. Minnich
parent
196ed499c1
commit
96bc60d84f
4 changed files with 322 additions and 13 deletions
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@ -11,6 +11,7 @@ CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"'
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CPUFLAGS += -DPIIX4_DEVFN=0x90
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CPUFLAGS += -DUPDATE_MICROCODE
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CPUFLAGS += -DCONFIGURE_L2_CACHE
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#CPUFLAGS += -DDEBUG
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LINUX=$(TOP)/../linux-2.4.0-test6.l440gx
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235
romimages/RON_L440GX_SCSI/Makefile
Normal file
235
romimages/RON_L440GX_SCSI/Makefile
Normal file
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@ -0,0 +1,235 @@
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CPUFLAGS=-DL440GX -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM
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CPUFLAGS += -D__KERNEL__
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CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD
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CPUFLAGS += -DSMP
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#CPUFLAGS += -DHAVE_FRAMEBUFFER
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DZKERNEL_START=0xfff40000
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CPUFLAGS += -DZKERNEL_MASK=0x3ed
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/sda1 console=ttyS0,115200 debug 3 single"'
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CPUFLAGS += -DPIIX4_DEVFN=0x90
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CPUFLAGS += -DUPDATE_MICROCODE
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CPUFLAGS += -DCONFIGURE_L2_CACHE
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#CPUFLAGS += -DDEBUG
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LINUX=$(TOP)/../linux-2.4.0-test6.l440gx.scsi
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include
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CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall
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OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o
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OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
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OBJECTS += southbridge.o northbridge.o
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#OBJECTS += pci.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += cpuid.o
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OBJECTS += serial_subr.o
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OBJECTS += mpspec.o
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OBJECTS += microcode.o
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OBJECTS += keyboard.o
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OBJECTS += l2_cache.o
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LINK = ld -T $(TOP)/src/mainboard/intel/l440gx/ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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# crt0 actually includes .inc files.
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# For self-documenting purposes, we put the FULL PATH of the
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# .inc files (relative to $TOP/src) in crt0.S.
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# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
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# To make this work, add the extra -I $(TOP)/src here.
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crt0.s: $(TOP)/src/mainboard/intel/l440gx/crt0.S
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$(CCASM) -I $(TOP)/src -E $< > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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mainboard.o: $(TOP)/src/mainboard/intel/l440gx/mainboard.c
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cc $(CFLAGS) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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southbridge.o: $(TOP)/src/southbridge/intel/piix4e/southbridge.c
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cc $(CFLAGS) -c $<
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northbridge.o: $(TOP)/src/northbridge/intel/440gx/northbridge.c
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cc $(CFLAGS) -c $<
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#superio.o: $(TOP)/src/superio/intel/950/superio.c
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# cc $(CFLAGS) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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l2_cache.o: $(TOP)/src/cpu/p6/l2_cache.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=640k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: $(LINUX)/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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rm -f docipl
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# here begins stupid stuff for the phlash program. It's ugly.
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#PHLASH_BASE_NAME=p11-0105
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PHLASH_BASE_NAME=p11-0102
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#PHLASH_BASE_NAME=p12-0115
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#PHLASH_BASE_NAME=p13-0125
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phlash: vmlinux.bin.gz linuxbios.rom headers
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rm -f xa?
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split -b 64k vmlinux.bin.gz
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# Now just touch them if we have a really
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# small kernel!
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touch xaa xab xac xad xae xaf xag xah
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# this if starting at bank 4, and proceeding on. Unused banks are dups
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# intel nvram is odd all of the banks are byte swapped
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cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1
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cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3
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cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2
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cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4
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cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7
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cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6
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cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9
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cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8
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cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia
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# Part o & 5 seem not to be written reliably for some reason...
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cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio
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cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5
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sh -x $(TOP)/src/mainboard/intel/l440gx/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME)
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headers: \
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$(PHLASH_BASE_NAME).bi1.header \
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$(PHLASH_BASE_NAME).bi2.header \
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$(PHLASH_BASE_NAME).bi3.header \
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$(PHLASH_BASE_NAME).bi4.header \
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$(PHLASH_BASE_NAME).bi5.header \
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$(PHLASH_BASE_NAME).bi6.header \
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$(PHLASH_BASE_NAME).bi7.header \
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$(PHLASH_BASE_NAME).bi8.header \
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$(PHLASH_BASE_NAME).bi9.header \
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$(PHLASH_BASE_NAME).bia.header \
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$(PHLASH_BASE_NAME).bio.header
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# This builds the headers from the intel flash disk.
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# we are not distributing this disk; you need to get it.
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BUILDHEADER=dd if=$< of=$@ bs=1 count=160
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$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio
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$(BUILDHEADER)
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@ -179,6 +179,7 @@ void pci_read_bases(struct pci_dev *dev, unsigned int howmany)
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addr &= (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK);
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if (addr == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
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DBG("reg %d is 64-bit\n", reg);
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/* this is a 64-bit memory base address */
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reg++;
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &addr);
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100
src/lib/newpci.c
100
src/lib/newpci.c
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@ -268,17 +268,31 @@ static const struct pci_ops *pci_check_direct(void)
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int pci_read_config_byte(struct pci_dev *dev, u8 where, u8 * val)
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{
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return conf->read_byte(dev->bus->number, dev->devfn, where, val);
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int res;
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res = conf->read_byte(dev->bus->number, dev->devfn, where, val);
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DBG("Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n",
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dev->bus->number, dev->devfn, where, *val, res);
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return res;
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}
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int pci_read_config_word(struct pci_dev *dev, u8 where, u16 * val)
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{
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return conf->read_word(dev->bus->number, dev->devfn, where, val);
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int res;
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res = conf->read_word(dev->bus->number, dev->devfn, where, val);
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DBG("Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n",
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dev->bus->number, dev->devfn, where, *val, res);
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return res;
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}
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int pci_read_config_dword(struct pci_dev *dev, u8 where, u32 * val)
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{
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return conf->read_dword(dev->bus->number, dev->devfn, where, val);
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int res;
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res = conf->read_dword(dev->bus->number, dev->devfn, where, val);
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DBG("Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n",
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dev->bus->number, dev->devfn, where, *val, res);
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return res;
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}
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int pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val)
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@ -290,7 +304,7 @@ int pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val)
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int pci_write_config_word(struct pci_dev *dev, u8 where, u16 val)
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{
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DBG("Write config byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
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DBG("Write config word bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
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dev->bus->number, dev->devfn, where, val);
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return conf->write_word(dev->bus->number, dev->devfn, where, val);
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@ -298,24 +312,38 @@ int pci_write_config_word(struct pci_dev *dev, u8 where, u16 val)
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int pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val)
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{
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DBG("Write config byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
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DBG("Write config dword bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
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dev->bus->number, dev->devfn, where, val);
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return conf->write_dword(dev->bus->number, dev->devfn, where, val);
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}
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int pcibios_read_config_byte(unsigned char bus, unsigned char devfn, u8 where, u8 * val)
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{
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return conf->read_byte(bus, devfn, where, val);
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int res;
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res = conf->read_byte(bus, devfn, where, val);
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DBG("Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n",
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bus, devfn, where, *val, res);
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return res;
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}
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int pcibios_read_config_word(unsigned char bus, unsigned char devfn, u8 where, u16 * val)
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{
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return conf->read_word(bus, devfn, where, val);
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int res;
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res = conf->read_word(bus, devfn, where, val);
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DBG("Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n",
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bus, devfn, where, *val, res);
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return res;
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}
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int pcibios_read_config_dword(unsigned char bus, unsigned char devfn, u8 where, u32 * val)
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{
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return conf->read_dword(bus, devfn, where, val);
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int res;
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res = conf->read_dword(bus, devfn, where, val);
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DBG("Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n",
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bus, devfn, where, *val, res);
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return res;
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}
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int pcibios_write_config_byte(unsigned char bus, unsigned char devfn, u8 where, u8 val)
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@ -424,7 +452,7 @@ void compute_allocate_io(struct pci_bus *bus)
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unsigned long io_base;
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io_base = bus->iobase;
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DBG("compute_allocate_mem: base 0x%lx\n", bus->iobase);
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DBG("compute_allocate_io: base 0x%lx\n", bus->iobase);
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/* First, walk all the bridges. When you return, grow the limit of the current bus
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since sub-busses need IO rounded to 4096 */
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@ -493,11 +521,30 @@ void compute_allocate_mem(struct pci_bus *bus)
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unsigned long size = curdev->size[i];
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unsigned long memorysize = size & (PCI_BASE_ADDRESS_MEM_MASK);
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unsigned long type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
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if (!memorysize)
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if (!memorysize) {
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continue;
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}
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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continue;
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}
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if (type == 0) {
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// we don't support the 1M type
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if (type & PCI_BASE_ADDRESS_MEM_TYPE_1M) {
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continue;
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}
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// if it's prefetch type, continue;
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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continue;
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}
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// now mask out all but the 32 or 64 bits
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type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
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// I'm pretty sure this test is not needed, but ...
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if ((type == PCI_BASE_ADDRESS_MEM_TYPE_32) ||
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(type == PCI_BASE_ADDRESS_MEM_TYPE_64)) {
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/* this is normal memory space */
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unsigned long regmem;
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@ -512,6 +559,10 @@ void compute_allocate_mem(struct pci_bus *bus)
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DBG("-->set base to 0x%lx\n", mem_base);
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mem_base += regmem;
|
||||
curdev->command |= PCI_COMMAND_MEMORY;
|
||||
// for 64-bit BARs, the odd ones don't count
|
||||
if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
|
||||
continue;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -553,8 +604,26 @@ void compute_allocate_prefmem(struct pci_bus *bus)
|
|||
if (!memorysize)
|
||||
continue;
|
||||
|
||||
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
||||
/* this is a prefetchable memory area */
|
||||
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
||||
continue;
|
||||
}
|
||||
|
||||
// we don't support the 1M type
|
||||
if (type & PCI_BASE_ADDRESS_MEM_TYPE_1M) {
|
||||
printk(__FUNCTION__ ": 1M memory not supported\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
// if it's not a prefetch type, continue;
|
||||
if (! (type & PCI_BASE_ADDRESS_MEM_PREFETCH))
|
||||
continue;
|
||||
// this should be a function some day ... comon code with
|
||||
// the non-prefetch allocate
|
||||
// now mask out all but the 32 or 64 bit type info
|
||||
type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
|
||||
// if all these names confuse you, they confuse me too!
|
||||
if ((type == PCI_BASE_ADDRESS_MEM_TYPE_32) ||
|
||||
(type == PCI_BASE_ADDRESS_MEM_TYPE_64)) {
|
||||
unsigned long regmem;
|
||||
|
||||
/* PCI BUS Spec suggests that the memory address should be
|
||||
|
|
@ -568,6 +637,9 @@ void compute_allocate_prefmem(struct pci_bus *bus)
|
|||
DBG("-->set base to 0x%lx\n", prefmem_base);
|
||||
prefmem_base += regmem;
|
||||
curdev->command |= PCI_COMMAND_MEMORY;
|
||||
// for 64-bit BARs, the odd ones don't count
|
||||
if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue