diff --git a/src/cpu/intel/haswell/Makefile.mk b/src/cpu/intel/haswell/Makefile.mk
index 41ca9c9d98..65e411df63 100644
--- a/src/cpu/intel/haswell/Makefile.mk
+++ b/src/cpu/intel/haswell/Makefile.mk
@@ -6,6 +6,7 @@ bootblock-y += ../car/bootblock.c
 bootblock-y += ../../x86/early_reset.S
 
 romstage-y += pcode_mailbox.c
+romstage-y += report_cpu_info.c
 romstage-y += romstage.c
 romstage-y += ../car/romstage.c
 
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index d24cbe1975..0a64149f28 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -172,6 +172,9 @@ int pcode_ready(void);
 u32 pcode_mailbox_read(u32 command);
 int pcode_mailbox_write(u32 command, u32 data);
 
+/* report_cpu_info.c */
+void report_cpu_info(void);
+
 /* CPU identification */
 static inline u32 cpu_family_model(void)
 {
diff --git a/src/cpu/intel/haswell/report_cpu_info.c b/src/cpu/intel/haswell/report_cpu_info.c
new file mode 100644
index 0000000000..9f93cd7002
--- /dev/null
+++ b/src/cpu/intel/haswell/report_cpu_info.c
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/msr.h>
+#include <string.h>
+#include <types.h>
+
+/* FIXME: Needs an update */
+static struct {
+	u32 cpuid;
+	const char *name;
+} cpu_table[] = {
+	{ CPUID_HASWELL_A0,       "Haswell A0" },
+	{ CPUID_HASWELL_B0,       "Haswell B0" },
+	{ CPUID_HASWELL_C0,       "Haswell C0" },
+	{ CPUID_HASWELL_ULT_B0,   "Haswell ULT B0" },
+	{ CPUID_HASWELL_ULT_C0,   "Haswell ULT C0 or D0" },
+	{ CPUID_CRYSTALWELL_C0,   "Haswell Perf Halo" },
+	{ CPUID_BROADWELL_ULT_C0, "Broadwell C0" },
+	{ CPUID_BROADWELL_ULT_D0, "Broadwell D0" },
+	{ CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" },
+};
+
+void report_cpu_info(void)
+{
+	static const char *const mode[] = {"NOT ", ""};
+	const char *cpu_type = "Unknown";
+
+	char cpu_string[50];
+	char *cpu_name = cpu_string; /* 48 bytes are reported */
+
+	const u32 index = 0x80000000;
+	struct cpuid_result cpuidr = cpuid(index);
+	if (cpuidr.eax < 0x80000004) {
+		strcpy(cpu_string, "Platform info not available");
+	} else {
+		u32 *p = (u32 *)cpu_string;
+		for (unsigned int i = 2; i <= 4; i++) {
+			cpuidr = cpuid(index + i);
+			*p++ = cpuidr.eax;
+			*p++ = cpuidr.ebx;
+			*p++ = cpuidr.ecx;
+			*p++ = cpuidr.edx;
+		}
+	}
+	/* Skip leading spaces in CPU name string */
+	while (cpu_name[0] == ' ')
+		cpu_name++;
+
+	const u32 cpu_id = cpu_get_cpuid();
+
+	/* Look for string to match the name */
+	for (unsigned int i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+		if (cpu_table[i].cpuid == cpu_id) {
+			cpu_type = cpu_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+	       cpu_id, cpu_type, get_current_microcode_rev());
+
+	const u32 cpu_feature_flag = cpu_get_feature_flags_ecx();
+	const bool aes = (cpu_feature_flag & CPUID_AES);
+	const bool txt = (cpu_feature_flag & CPUID_SMX);
+	const bool vt  = (cpu_feature_flag & CPUID_VMX);
+	printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+	       mode[aes], mode[txt], mode[vt]);
+}
diff --git a/src/northbridge/intel/broadwell/report_platform.c b/src/northbridge/intel/broadwell/report_platform.c
index 2f5293a3e2..311ab35081 100644
--- a/src/northbridge/intel/broadwell/report_platform.c
+++ b/src/northbridge/intel/broadwell/report_platform.c
@@ -1,10 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <cpu/intel/haswell/haswell.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/x86/msr.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <soc/pch.h>
@@ -13,22 +10,6 @@
 #include <soc/systemagent.h>
 #include <string.h>
 
-/* FIXME: Needs an update */
-static struct {
-	u32 cpuid;
-	const char *name;
-} cpu_table[] = {
-	{ CPUID_HASWELL_A0,       "Haswell A0" },
-	{ CPUID_HASWELL_B0,       "Haswell B0" },
-	{ CPUID_HASWELL_C0,       "Haswell C0" },
-	{ CPUID_HASWELL_ULT_B0,   "Haswell ULT B0" },
-	{ CPUID_HASWELL_ULT_C0,   "Haswell ULT C0 or D0" },
-	{ CPUID_CRYSTALWELL_C0,   "Haswell Perf Halo" },
-	{ CPUID_BROADWELL_ULT_C0, "Broadwell C0" },
-	{ CPUID_BROADWELL_ULT_D0, "Broadwell D0" },
-	{ CPUID_BROADWELL_ULT_E0, "Broadwell E0 or F0" },
-};
-
 static struct {
 	u8 revid;
 	const char *name;
@@ -72,54 +53,6 @@ static struct {
 	{ IGD_BROADWELL_H_GT3,     "Broadwell U GT3" },
 };
 
-static void report_cpu_info(void)
-{
-	static const char *const mode[] = {"NOT ", ""};
-	const char *cpu_type = "Unknown";
-
-	char cpu_string[50];
-	char *cpu_name = cpu_string; /* 48 bytes are reported */
-
-	const u32 index = 0x80000000;
-	struct cpuid_result cpuidr = cpuid(index);
-	if (cpuidr.eax < 0x80000004) {
-		strcpy(cpu_string, "Platform info not available");
-	} else {
-		u32 *p = (u32 *)cpu_string;
-		for (unsigned int i = 2; i <= 4; i++) {
-			cpuidr = cpuid(index + i);
-			*p++ = cpuidr.eax;
-			*p++ = cpuidr.ebx;
-			*p++ = cpuidr.ecx;
-			*p++ = cpuidr.edx;
-		}
-	}
-	/* Skip leading spaces in CPU name string */
-	while (cpu_name[0] == ' ')
-		cpu_name++;
-
-	const u32 cpu_id = cpu_get_cpuid();
-
-	/* Look for string to match the name */
-	for (unsigned int i = 0; i < ARRAY_SIZE(cpu_table); i++) {
-		if (cpu_table[i].cpuid == cpu_id) {
-			cpu_type = cpu_table[i].name;
-			break;
-		}
-	}
-
-	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
-	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
-	       cpu_id, cpu_type, get_current_microcode_rev());
-
-	const u32 cpu_feature_flag = cpu_get_feature_flags_ecx();
-	const bool aes = (cpu_feature_flag & CPUID_AES);
-	const bool txt = (cpu_feature_flag & CPUID_SMX);
-	const bool vt  = (cpu_feature_flag & CPUID_VMX);
-	printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
-	       mode[aes], mode[txt], mode[vt]);
-}
-
 static void report_mch_info(void)
 {
 	const u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 28d2f01323..1227292a0c 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -9,7 +9,7 @@
 #include <cpu/x86/msr.h>
 #include "haswell.h"
 
-static void report_cpu_info(void)
+static void haswell_report_cpu_info(void)
 {
 	struct cpuid_result cpuidr;
 	u32 i, index, cpu_id, cpu_feature_flag;
@@ -96,6 +96,6 @@ static void report_pch_info(void)
 
 void report_platform_info(void)
 {
-	report_cpu_info();
+	haswell_report_cpu_info();
 	report_pch_info();
 }