Added changes to the ram initialization based on Intel's Documentation.
Added PCI bus parity checking on data and address lines. Errors will cause a NMI.
This commit is contained in:
Tom Zimmerman
parent
9083c87977
commit
9648966b58
5 changed files with 278 additions and 130 deletions
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@ -8,3 +8,4 @@ mainboardinit sdram/generic_sdram.inc
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mainboardinit sdram/generic_cache_linuxbios.inc
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object northbridge.o
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object pci_parity.o
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28
src/northbridge/intel/E7500/pci_parity.c
Normal file
28
src/northbridge/intel/E7500/pci_parity.c
Normal file
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@ -0,0 +1,28 @@
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#include <mem.h>
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#include <pci.h>
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#include <arch/io.h>
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#include <printk.h>
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#
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void e7500_pci_parity_enable(void)
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{
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uint8_t reg;
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/* Generate an SERR when a HI_A parity error is detected */
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pcibios_read_config_byte(0, ((0 << 3) + (1 << 0)), 0x5c, ®);
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reg |= ((1 << 4) + (1 << 0));
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pcibios_write_config_byte(0, ((0 << 3) + (1 << 0)), 0x5c, reg);
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/* Enable SERR on system bus errors */
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pcibios_read_config_byte(0, ((0 << 3) + (1 << 0)), 0x6c, ®);
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reg |= ((1 << 3) + (1 << 2) + (1 << 1) + (1 << 0));
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pcibios_write_config_byte(0, ((0 << 3) + (1 << 0)), 0x6c, reg);
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/* 2SERREN - SERR message forwarding from HI_B to HI_A */
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/* 2PEREN - Parity error response enable HI_B */
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pcibios_read_config_byte(0, ((2 << 3) + (0 << 0)), 0x3e, ®);
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reg |= ((1 << 1) + (1 << 0));
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pcibios_write_config_byte(0, ((2 << 3) + (0 << 0)), 0x3e, reg);
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return;
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}
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@ -8,3 +8,4 @@ mainboardinit sdram/generic_sdram.inc
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mainboardinit sdram/generic_cache_linuxbios.inc
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object northbridge.o
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object pci_parity.o
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28
src/northbridge/intel/E7501/pci_parity.c
Normal file
28
src/northbridge/intel/E7501/pci_parity.c
Normal file
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@ -0,0 +1,28 @@
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#include <mem.h>
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#include <pci.h>
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#include <arch/io.h>
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#include <printk.h>
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#
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void e7501_pci_parity_enable(void)
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{
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uint8_t reg;
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/* Generate an SERR when a HI_A parity error is detected */
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pcibios_read_config_byte(0, ((0 << 3) + (1 << 0)), 0x5c, ®);
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reg |= ((1 << 4) + (1 << 0));
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pcibios_write_config_byte(0, ((0 << 3) + (1 << 0)), 0x5c, reg);
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/* Enable SERR on system bus errors */
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pcibios_read_config_byte(0, ((0 << 3) + (1 << 0)), 0x6c, ®);
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reg |= ((1 << 3) + (1 << 2) + (1 << 1) + (1 << 0));
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pcibios_write_config_byte(0, ((0 << 3) + (1 << 0)), 0x6c, reg);
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/* 2SERREN - SERR message forwarding from HI_B to HI_A */
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/* 2PEREN - Parity error response enable HI_B */
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pcibios_read_config_byte(0, ((2 << 3) + (0 << 0)), 0x3e, ®);
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reg |= ((1 << 1) + (1 << 0));
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pcibios_write_config_byte(0, ((2 << 3) + (0 << 0)), 0x3e, reg);
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return;
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}
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@ -11,7 +11,7 @@ jmp intel_E7501_out
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* Steven James 02/06/2003
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*/
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#define DEBUG_RAM_CONFIG 1
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#define DEBUG_RAM_CONFIG 0
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/* DDR DIMM Mode register Definitions */
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@ -34,7 +34,8 @@ jmp intel_E7501_out
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#define BURST_LENGTH BURST_4
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#define BURST_TYPE BURST_INTERLEAVED
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#define CAS_LATENCY CAS_2_5
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#define CAS_LATENCY CAS_2_0
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//#define CAS_LATENCY CAS_2_5
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//#define CAS_LATENCY CAS_1_5
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#define MRS_VALUE (MODE_NORM | CAS_LATENCY | BURST_TYPE | BURST_LENGTH)
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@ -196,17 +197,10 @@ constant_register_values:
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*/
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#if CAS_LATENCY == CAS_2_5
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# .long 0x80, 0xfffffe00, 0x06 /* Intel E7500 recommended */
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# .long 0x80, 0xfffff000, 0x0bb6 /* Intel E7500 recommended */
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# .long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
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.long 0x80, 0xfffff000, 0x0bb1 /* values for register 0x80 */
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.long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
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#elif CAS_LATENCY == CAS_2_0
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# .long 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
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.long 0x80, 0xfffff000, 0x0bb1 /* values for register 0x80 */
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# .long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
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#elif CAS_LATENCY == CAS_1_5
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# .long 0x80, 0xfffffe00, 0x05
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# .long 0x80, 0xfffff000, 0x0bb5
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.long 0x80, 0xfffff000, 0x0662 /* from Factory Bios */
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#endif
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/* Enable periodic memory recalibration */
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@ -373,7 +367,7 @@ constant_register_values:
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* 11 == Reserved
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* [19:18] Reserved
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* Must equal 01
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* [17:17] Reserved Intel BIOS sets this to 1
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* [17:17] (Intel Undocumented) should always be set to 1
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* [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
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* 0 == 2n Rule
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* 1 == 1n rule
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@ -398,8 +392,13 @@ constant_register_values:
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*/
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# .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8)
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# .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8)
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// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8)
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.long 0x7c, 0xff82fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 16)| (0 << 8)
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/* Another Intel undocumented register */
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.long 0x88, 0x080007ff, (1<<31)|(1 << 30)|(1<<28)|(0 << 26)|(0x10 << 21)|(10 << 16)|(0x13 << 11)
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/* CLOCK_DIS - CK/CK# Disable Register
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* 0x8C
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* [7:4] Reserved
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@ -458,6 +457,9 @@ constant_register_values:
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* 1 == Absent
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*/
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.long 0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0)
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.long 0xd8, 0xffff9fff, 0x00000000
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.long 0xf4, 0x3f8ffffd, 0x40300002
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.long 0x1050, 0xffffffcf, 0x00000030
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constant_register_values_end:
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@ -474,126 +476,154 @@ constant_register_values_end:
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* Which are a triple of configuration regiser, mask, and value.
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*
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*/
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/* DDR RECOMP/SCOMP table */
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#define RCOMP_MMIO 0x080000
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/* DDR RECOMP table */
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.p2align 3
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ddr_rcomp_scomp_table:
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/* register, function 2, function 3 */
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.long 0x054, 0x000000000, 0x000000000
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.long 0x058, 0x076433221, 0x076433221
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.long 0x05c, 0x0fedca988, 0x0fedca988
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.long 0x060, 0x0ffffffff, 0x0ffffffff
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.long 0x064, 0x000000000, 0x000000000
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.long 0x068, 0x076433221, 0x076433221
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.long 0x06c, 0x0fedca988, 0x0fedca988
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.long 0x070, 0x0ffffffff, 0x0ffffffff
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.long 0x084, 0x000000000, 0x099999999
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.long 0x088, 0x076433221, 0x099999999
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.long 0x08c, 0x0fedca988, 0x099999999
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.long 0x090, 0x0ffffffff, 0x099999999
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.long 0x094, 0x000000000, 0x0aaaaaaaa
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.long 0x098, 0x076433221, 0x0aaaaaaaa
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.long 0x09c, 0x0fedca988, 0x0aaaaaaaa
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.long 0x0a0, 0x0ffffffff, 0x0aaaaaaaa
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.long 0x0b4, 0x000000000, 0x000000000
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.long 0x0b8, 0x076433221, 0x076433221
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.long 0x0bc, 0x0fedca988, 0x0fedca988
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.long 0x0c0, 0x0ffffffff, 0x0ffffffff
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.long 0x0c4, 0x000000000, 0x000000000
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.long 0x0c8, 0x076433221, 0x076433221
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.long 0x0cc, 0x0fedca988, 0x0fedca988
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.long 0x0d0, 0x0ffffffff, 0x0ffffffff
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ddr_rcomp_scomp_table_end:
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ddr_rcomp_1:
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.long 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff
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.long 0x22111111, 0x55444332, 0xfffca876, 0xffffffff
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ddr_rcomp_2:
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.long 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff
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.long 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff
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ddr_rcomp_3:
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.long 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
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.long 0x88888888, 0x88888888, 0x88888888, 0x88888888
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.p2align 3
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ram_set_registers:
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CALL_LABEL(ram_set_rcomp_regs)
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CALL_LABEL(ram_set_d0f0_regs)
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RET_LABEL(ram_set_registers)
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rcomp_init_str: .string "Setting RCOMP registers.\r\n"
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write_8dwords:
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mov %esp, %ebp
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movl %ecx, %edx
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addl $32, %edx
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1: movl (%ecx), %eax
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movl %eax, (%ebx)
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addl $4, %ecx
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addl $4, %ebx
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cmpl %ecx, %edx
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jnz 1b
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subl $32, %ecx
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mov %ebp, %esp
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RETSP
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ram_set_rcomp_regs:
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movl $0x0e0, %eax /*enable device 0 functions 2 & 3 */
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PCI_READ_CONFIG_BYTE
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andb $~(1<<1), %al
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movb %al, %dl /* Put data in dl */
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movl $0x0e0, %eax /* write to offset e0 */
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PCI_WRITE_CONFIG_BYTE
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/* load the tables in device 0 functions 2 and 3 */
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movl $ddr_rcomp_scomp_table, %ebx
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1: movl 0(%ebx), %eax /* get the register address */
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orl $0x200, %eax /* set to function 2 */
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movl 4(%ebx), %ecx /* get the data for function 2 */
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PCI_WRITE_CONFIG_DWORD
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movl 0(%ebx), %eax /* get the register address */
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orl $0x300, %eax /* set to function 3 */
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movl 8(%ebx), %ecx /* get the data for function 3 */
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PCI_WRITE_CONFIG_DWORD
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addl $12, %ebx
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cmpl $ddr_rcomp_scomp_table_end, %ebx
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jb 1b
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CONSOLE_INFO_TX_STRING($rcomp_init_str)
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movl $0x088, %eax /* RCOMP evaluation phase */
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PCI_READ_CONFIG_BYTE
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andb $~(1<<5), %al
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movb %al, %dl /* Put data in dl */
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movb %al, %cl /* save the byte */
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movl $0x088, %eax /* write to offset 88 */
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PCI_WRITE_CONFIG_BYTE
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orb $(1<<5), %cl
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movb %cl, %dl /* Put data in dl */
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movl $0x088, %eax /* write to offset 88 */
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PCI_WRITE_CONFIG_BYTE
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2: movl $0x088, %eax /* poll for RCOMP evaluation complete */
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PCI_READ_CONFIG_BYTE
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andb $(1<<5), %al
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jnz 2b
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movl $0x088, %eax /* RCOMP/SCOMP register update */
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PCI_READ_CONFIG_BYTE
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andb $~(1<<6), %al
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movb %al, %dl /* Put data in dl */
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movb %al, %cl /* save the byte */
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movl $0x088, %eax /* write to offset 88 */
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PCI_WRITE_CONFIG_BYTE
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orb $(1<<6), %cl
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movb %cl, %dl /* Put data in dl */
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movl $0x088, %eax /* write to offset 88 */
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PCI_WRITE_CONFIG_BYTE
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3: movl $0x088,%eax /* poll for RCOMP/SCOMP update complete */
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PCI_READ_CONFIG_BYTE
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andb $(1<<6), %al
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jnz 3b
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/* place the command clock drive strength comp in static override */
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movl $0x0380, %eax /* read function 3 offset 80 */
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movl $0x0f4, %eax /*enable access to the rcomp bar */
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PCI_READ_CONFIG_DWORD
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/* not sure this next section is correct, documentation on device 0
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function 3, register 80 is lacking. */
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movl %eax, %ecx
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andl $~(1<<31), %eax
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orl $((1<<30)|(1<<22)), %eax
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movl %eax, %ecx /* Put data in ecx */
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movl $0x0f4, %eax /* write to offset f4 */
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PCI_WRITE_CONFIG_DWORD
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andl $0xff01ffff, %ecx
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shrl $7, %eax
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andl $0x00fe0000, %eax
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orl %eax, %ecx
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movl $0x0380, %eax
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PCI_WRITE_CONFIG_DWORD /* Set pull up values */
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movl %ecx, %eax
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andl $0xffffff01, %ecx
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shrl $7, %eax
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andl $0x000000fe, %eax
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orl %eax, %ecx
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movl $0x0380, %eax
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PCI_WRITE_CONFIG_DWORD /* Set pull down values */
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orl $0x80008000, %ecx
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movl $0x0380, %eax
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PCI_WRITE_CONFIG_DWORD /* enable mode overide */
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/* Set the MMIO address to 512K */
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movl $RCOMP_MMIO, %ecx
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movl $0x14, %eax
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PCI_WRITE_CONFIG_DWORD
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movl $(RCOMP_MMIO + 0x20), %ecx
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movl (%ecx), %eax
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orl $(1<<9), %eax
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movl %eax, (%ecx)
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/* Begin to write the RCOMP registers */
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movl $(RCOMP_MMIO + 0x2c), %ebx
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movb $0xff, (%ebx)
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movl $(RCOMP_MMIO + 0x30), %ebx
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movl $0x01040444, (%ebx)
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movl $(RCOMP_MMIO + 0x34), %ebx
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movb $0x04, (%ebx)
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movl $(RCOMP_MMIO + 0x40), %ebx
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xorl %eax, %eax
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movl %eax, (%ebx)
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movb $0x44, %bl
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movw %ax, (%ebx)
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movb $0x48, %bl
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movw %ax, (%ebx)
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movb $0x4c, %bl
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movw %ax, (%ebx)
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movb $0x50, %bl
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movw %ax, (%ebx)
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movl $(RCOMP_MMIO + 0x60), %ebx
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movl $ddr_rcomp_1, %ecx
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CALLSP(write_8dwords)
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movl $(RCOMP_MMIO + 0x80), %ebx
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movl $ddr_rcomp_2, %ecx
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CALLSP(write_8dwords)
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movl $(RCOMP_MMIO + 0xa0), %ebx
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CALLSP(write_8dwords)
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movl $(RCOMP_MMIO + 0x140), %ebx
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CALLSP(write_8dwords)
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movl $(RCOMP_MMIO + 0x1c0), %ebx
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CALLSP(write_8dwords)
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movl $(RCOMP_MMIO + 0x180), %ebx
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movl $ddr_rcomp_3, %ecx
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CALLSP(write_8dwords)
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#if 0 /* Print the RCOMP registers */
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movl $RCOMP_MMIO, %ecx
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1: movl %ecx, %eax
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andb $0x0f, %al
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jnz 2f
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CONSOLE_INFO_TX_CHAR($'\r')
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CONSOLE_INFO_TX_CHAR($'\n')
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CONSOLE_INFO_TX_HEX32(%ecx)
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CONSOLE_INFO_TX_CHAR($' ')
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CONSOLE_INFO_TX_CHAR($'-')
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CONSOLE_INFO_TX_CHAR($' ')
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2: movl (%ecx), %eax
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CONSOLE_INFO_TX_HEX32(%eax)
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CONSOLE_INFO_TX_CHAR($' ')
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addl $4, %ecx
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cmpl $(RCOMP_MMIO + 0x1e0), %ecx
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jnz 1b
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CONSOLE_INFO_TX_CHAR($'\r')
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CONSOLE_INFO_TX_CHAR($'\n')
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#endif
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movl $(RCOMP_MMIO + 0x20), %ecx
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movl (%ecx), %eax
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andl $~(3), %eax
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orl $(1), %eax
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movl %eax, (%ecx)
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/* Wait 40 usec */
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SLOW_DOWN_IO
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/* unblock updates */
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movl $(RCOMP_MMIO + 0x20), %ecx
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movl (%ecx), %eax
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andl $~(1<<9), %eax
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movl %eax, (%ecx)
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orl $(1<<8), %eax
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movl %eax, (%ecx)
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andl $~(1<<8), %eax
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movl %eax, (%ecx)
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/* Wait 40 usec */
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SLOW_DOWN_IO
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movl $0x0f4, %eax /*disable access to the rcomp bar */
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PCI_READ_CONFIG_DWORD
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andl $~(1<<22), %eax
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movl %eax, %ecx /* Put data in ecx */
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movl $0x0f4, %eax /* write to offset f4 */
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PCI_WRITE_CONFIG_DWORD
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movl $0x0088, %eax /* enable periodic compensaion */
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PCI_READ_CONFIG_BYTE
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orb $(1<<7), %al
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mov %al, %dl
|
||||
movl $0x0088, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
RET_LABEL(ram_set_rcomp_regs)
|
||||
|
||||
|
||||
ram_set_d0f0_regs:
|
||||
#if DEBUG_RAM_CONFIG
|
||||
CALLSP(dumpnorth)
|
||||
|
|
@ -1389,8 +1419,11 @@ cas_latency_80:
|
|||
|
||||
# .byte 0x05, 0x01, 0x06
|
||||
# .byte 0xb5, 0xb1, 0xb6
|
||||
# .byte 0x62, 0x62, 0x62 /* factory setting for 0 undocumented reg tnz */
|
||||
.byte 0xb1, 0xb1, 0xb1 /* factory setting for 0 undocumented reg tnz */
|
||||
.word 0x0, 0x0bb1, 0x0662 /* RCVEN */
|
||||
cas_latency_80_4dimms:
|
||||
.word 0x0, 0x0bb1, 0x0882
|
||||
|
||||
|
||||
cas_latency_78:
|
||||
.byte DRT_CAS_1_5, DRT_CAS_2_0, DRT_CAS_2_5
|
||||
|
||||
|
|
@ -1492,6 +1525,7 @@ spd_set_cas_latency_next_dimm:
|
|||
movl $0x88, %eax /* set master DLL reset */
|
||||
PCI_READ_CONFIG_DWORD
|
||||
orl $(1<<26), %eax
|
||||
shll $1, %ecx /* the rest of the references are words */
|
||||
movl %ecx, %ebx
|
||||
movl %eax, %ecx
|
||||
movl $0x88, %eax
|
||||
|
|
@ -1507,15 +1541,35 @@ spd_set_cas_latency_next_dimm:
|
|||
PCI_WRITE_CONFIG_DWORD
|
||||
movl %ebx, %ecx
|
||||
movl $0x80, %eax
|
||||
movb cas_latency_80(%ecx), %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
PCI_READ_CONFIG_WORD
|
||||
andl $~(0x0fff), %eax
|
||||
movl %eax, %ebx
|
||||
orw cas_latency_80(%ecx), %bx
|
||||
movl $0x70, %eax
|
||||
PCI_READ_CONFIG_DWORD
|
||||
andb $0xff, %al
|
||||
jz 1f
|
||||
shrl $8, %eax
|
||||
andb $0xff, %al
|
||||
jz 1f
|
||||
shrl $8, %eax
|
||||
andb $0xff, %al
|
||||
jz 1f
|
||||
shrl $8, %eax
|
||||
andb $0xff, %al
|
||||
jz 1f
|
||||
andl $~(0x0fff), %ebx /* we have dimms in all 4 slots */
|
||||
orw cas_latency_80_4dimms(%ecx), %bx
|
||||
1: movl %ebx, %ecx
|
||||
movl $0x80, %eax
|
||||
PCI_WRITE_CONFIG_WORD
|
||||
movl $0x88, %eax /* reset master DLL reset */
|
||||
PCI_READ_CONFIG_DWORD
|
||||
andl $~(1<<26), %eax
|
||||
movl %eax, %ecx
|
||||
movl $0x88, %eax
|
||||
PCI_WRITE_CONFIG_DWORD
|
||||
|
||||
RAM_RESET_DDR_PTR()
|
||||
RET_LABEL(spd_set_cas_latency)
|
||||
|
||||
spd_set_dram_timing:
|
||||
|
|
@ -1569,7 +1623,14 @@ spd_get_dram_timing:
|
|||
subb $1, %al
|
||||
andl $0xff, %eax /* Clear the upper bits of eax */
|
||||
divb %dl, %al
|
||||
|
||||
#if 0
|
||||
CONSOLE_DEBUG_TX_HEX32(%eax)
|
||||
CONSOLE_DEBUG_TX_CHAR($'-')
|
||||
CONSOLE_DEBUG_TX_CHAR($'x')
|
||||
CONSOLE_DEBUG_TX_CHAR($'7')
|
||||
CONSOLE_DEBUG_TX_CHAR($'8')
|
||||
jmp 1f
|
||||
#endif
|
||||
/* Don't even process small timings */
|
||||
cmpb $5, %al
|
||||
jbe 1f
|
||||
|
|
@ -1587,6 +1648,7 @@ spd_get_dram_timing:
|
|||
andl $3, %ecx
|
||||
notl %ecx
|
||||
subl $1, %ecx
|
||||
andl $3, %ecx
|
||||
|
||||
/* See if we need a slower timing */
|
||||
cmpb %cl, %al
|
||||
|
|
@ -1596,6 +1658,7 @@ spd_get_dram_timing:
|
|||
movb %al, %cl
|
||||
addb $1, %cl
|
||||
notl %ecx
|
||||
andl $3, %ecx
|
||||
shll $9, %ecx
|
||||
andl $~(3<<9), %esi
|
||||
orl %ecx, %esi
|
||||
|
|
@ -1604,35 +1667,54 @@ spd_get_dram_timing:
|
|||
/*
|
||||
* tRD
|
||||
*/
|
||||
/* Set to a 7 clock read delay */
|
||||
andl $~(7<<24), %esi
|
||||
/* Set to a 7 clock read delay. This is for 133Mhz
|
||||
* with a CAS latency of 2.5 if 2.0 a 6 clock
|
||||
* delay is good */
|
||||
movl $0x78, %eax
|
||||
PCI_READ_CONFIG_BYTE
|
||||
andb $0x30, %al
|
||||
jnz 1f
|
||||
andl $~(7<<24), %esi /* CAS latency is 2.5, make 7 clks */
|
||||
|
||||
/*
|
||||
* Back to Back Read Turn Around
|
||||
*/
|
||||
/* Set to a 4 clock back to back read turn around */
|
||||
# andl $~(1<<27), %esi
|
||||
/* Set to a 3 clock back to back read turn around. This
|
||||
* is good for CAS latencys 2.5 and 2.0 */
|
||||
1: orl $(1<<27), %esi
|
||||
/*
|
||||
* Back to Back Read-Write Turn Around
|
||||
*/
|
||||
/* Set to a 5 clock back to back read to write turn around */
|
||||
/* Set to a 5 clock back to back read to write turn around.
|
||||
* 4 is a good delay if the CAS latency is 2.0 */
|
||||
movl $0x78, %eax
|
||||
PCI_READ_CONFIG_BYTE
|
||||
and $(1<<4), %al
|
||||
jnz 2f
|
||||
andl $~(1<<28), %esi
|
||||
/*
|
||||
* Back to Back Write-Read Turn Around
|
||||
*/
|
||||
/* Set to a 3 clock back to back write to read turn around */
|
||||
# andl $~(1<<29), %esi
|
||||
|
||||
/* Set to a 2 clock back to back write to read turn around.
|
||||
* This is good for 2.5 and 2.0 CAS Latencies. */
|
||||
2: orl $(1<<29), %esi
|
||||
spd_set_dram_timing_next_dimm:
|
||||
#if 1
|
||||
/* go to the next DIMM */
|
||||
addb $(SMBUS_MEM_DEVICE_INC), %bl /* increment the smbus device */
|
||||
cmpb $SMBUS_MEM_DEVICE_END, %bl
|
||||
jbe spd_get_dram_timing
|
||||
|
||||
#endif
|
||||
movl $0x78, %eax
|
||||
movl %esi, %ecx
|
||||
PCI_WRITE_CONFIG_DWORD
|
||||
|
||||
#if 0
|
||||
CONSOLE_DEBUG_TX_HEX32(%ecx)
|
||||
CONSOLE_DEBUG_TX_CHAR($'-')
|
||||
CONSOLE_DEBUG_TX_CHAR($'x')
|
||||
CONSOLE_DEBUG_TX_CHAR($'7')
|
||||
CONSOLE_DEBUG_TX_CHAR($'8')
|
||||
#endif
|
||||
RET_LABEL(spd_set_dram_timing)
|
||||
|
||||
|
||||
|
|
@ -1889,9 +1971,17 @@ dram_finish:
|
|||
|
||||
noecc_init:
|
||||
|
||||
movl $0x7c, %eax /* FCS_EN */
|
||||
PCI_READ_CONFIG_DWORD
|
||||
orl $(1<<17), %eax
|
||||
movl %eax, %ecx
|
||||
movl $0x7c, %eax
|
||||
PCI_WRITE_CONFIG_DWORD
|
||||
|
||||
#if DEBUG_RAM_CONFIG
|
||||
CALLSP(dumpnorth)
|
||||
#endif
|
||||
|
||||
CALL_LABEL(verify_ram)
|
||||
RET_LABEL(dram_finish)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue