From 953957e9613b8eddf3a983cb6e205de6ea8ae1a4 Mon Sep 17 00:00:00 2001 From: Luca Lai Date: Fri, 25 Jul 2025 09:34:34 +0800 Subject: [PATCH] mb/google/trulo/var/pujjolo: Change ICCmax at VCCIN_AUX from 25A to 27A Becasue of requirement for VCCANA power from MBVR mode to FIVR mode, so change ICCmax at VCCIN_AUX will be from 25A to 27A due to internal VR. BUG=b:417662158 TEST=Build and boot to OS at the rework motherboard and verfied by power team. Change-Id: Ie036412c0e435cfce39940de6bab363f9e875f42 Signed-off-by: Luca Lai Reviewed-on: https://review.coreboot.org/c/coreboot/+/88558 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- .../google/brya/variants/pujjolo/Makefile.mk | 1 + src/mainboard/google/brya/variants/pujjolo/ramstage.c | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 src/mainboard/google/brya/variants/pujjolo/ramstage.c diff --git a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk index 98cf9a8419..4a6700c6ec 100644 --- a/src/mainboard/google/brya/variants/pujjolo/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjolo/Makefile.mk @@ -6,4 +6,5 @@ romstage-y += memory.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/pujjolo/ramstage.c b/src/mainboard/google/brya/variants/pujjolo/ramstage.c new file mode 100644 index 0000000000..5cb79a81b9 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjolo/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Refer to FSP Silicon (soc/intel/alderlake/fsp_params.c) + VccIn Aux Imon IccMax. Values are in 1/4 Amp increments */ + params->VccInAuxImonIccImax = 108; /* 30000(30A) * 4 / 1000 */ + printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax); +}