From 94dd3f3bba296822ecef6e8470f4e641dbaeb5e2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 23 Mar 2026 14:06:44 +0530 Subject: [PATCH] soc/qualcomm/x1p42100: Increase boot CPU frequency to 3.0GHz Boost the initial CPU frequency from 1.36GHz to ~3.0GHz (2995.2 MHz) during the boot phase to reduce the execution time of ramstage and subsequent payload loading. Changes: - clock.h: Add L_VAL_2995P2MHz (0x9C) based on a 19.2MHz XO. - clock.c: Update speed_up_boot_cpu() to use the 3.0GHz PLL multiplier for the APSS NCC0 clock. This change helps in further optimizing the boot timeline, leveraging the higher clock speed for faster initialization. BUG=b:449871690 TEST=Able to save ~50ms of the boot time (mostly during Qclib). Change-Id: I459001717298b10201c3b3c8bf6b0c20097ae830 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/91818 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Jayvik Desai --- src/soc/qualcomm/x1p42100/clock.c | 6 +++--- src/soc/qualcomm/x1p42100/include/soc/clock.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c index 76e964831f..9adbe230d1 100644 --- a/src/soc/qualcomm/x1p42100/clock.c +++ b/src/soc/qualcomm/x1p42100/clock.c @@ -697,9 +697,9 @@ void enable_disp_clock_tcsr(void) static void speed_up_boot_cpu(void) { - /* 1363.2 MHz */ - if (!pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz)) - printk(BIOS_DEBUG, "NCC Frequency bumped to 1.363(GHz)\n"); + /* 3 GHz */ + if (!pll_init_and_set(apss_ncc0, L_VAL_2995P2MHz)) + printk(BIOS_DEBUG, "NCC Frequency bumped to 3.0(GHz)\n"); } void clock_init(void) diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h index 474852940b..934c0fdb34 100644 --- a/src/soc/qualcomm/x1p42100/include/soc/clock.h +++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h @@ -19,6 +19,7 @@ #define CLK_37_5MHZ (37.5 * MHz) /* CPU PLL*/ +#define L_VAL_2995P2MHz 0x9C #define L_VAL_1363P2MHz 0x47 #define L_VAL_806MHz 0x2A