diff --git a/src/soc/qualcomm/x1p42100/clock.c b/src/soc/qualcomm/x1p42100/clock.c
index 76e964831f..9adbe230d1 100644
--- a/src/soc/qualcomm/x1p42100/clock.c
+++ b/src/soc/qualcomm/x1p42100/clock.c
@@ -697,9 +697,9 @@ void enable_disp_clock_tcsr(void)
 
 static void speed_up_boot_cpu(void)
 {
-	/* 1363.2 MHz */
-	if (!pll_init_and_set(apss_ncc0, L_VAL_1363P2MHz))
-		printk(BIOS_DEBUG, "NCC Frequency bumped to 1.363(GHz)\n");
+	/* 3 GHz */
+	if (!pll_init_and_set(apss_ncc0, L_VAL_2995P2MHz))
+		printk(BIOS_DEBUG, "NCC Frequency bumped to 3.0(GHz)\n");
 }
 
 void clock_init(void)
diff --git a/src/soc/qualcomm/x1p42100/include/soc/clock.h b/src/soc/qualcomm/x1p42100/include/soc/clock.h
index 474852940b..934c0fdb34 100644
--- a/src/soc/qualcomm/x1p42100/include/soc/clock.h
+++ b/src/soc/qualcomm/x1p42100/include/soc/clock.h
@@ -19,6 +19,7 @@
 #define CLK_37_5MHZ		(37.5 * MHz)
 
 /* CPU PLL*/
+#define L_VAL_2995P2MHz		0x9C
 #define L_VAL_1363P2MHz		0x47
 #define L_VAL_806MHz		0x2A