From 947dd078232a6f0f58603926063cee3b085b46f9 Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Sat, 10 May 2025 16:49:28 -0500
Subject: [PATCH] soc/intel/jasperlake: Hook up IGD config to option API

Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.

Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for other SoCs.

Change-Id: Id85e698263b0193d0a83cd4d6ee6c10c89a1d2fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87623
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/chip.h               | 30 +++++++++++++++++++
 .../intel/jasperlake/romstage/fsp_params.c    | 15 ++++++----
 2 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 408cdcfa46..380549451e 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -57,6 +57,36 @@ static const struct {
 	{ PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W },
 };
 
+/* Gfx related */
+enum igd_dvmt50_pre_alloc {
+	IGD_SM_0MB = 0x00,
+	IGD_SM_32MB = 0x01,
+	IGD_SM_64MB = 0x02,
+	IGD_SM_96MB = 0x03,
+	IGD_SM_128MB = 0x04,
+	IGD_SM_160MB = 0x05,
+	IGD_SM_4MB = 0xF0,
+	IGD_SM_8MB = 0xF1,
+	IGD_SM_12MB = 0xF2,
+	IGD_SM_16MB = 0xF3,
+	IGD_SM_20MB = 0xF4,
+	IGD_SM_24MB = 0xF5,
+	IGD_SM_28MB = 0xF6,
+	IGD_SM_36MB = 0xF8,
+	IGD_SM_40MB = 0xF9,
+	IGD_SM_44MB = 0xFA,
+	IGD_SM_48MB = 0xFB,
+	IGD_SM_52MB = 0xFC,
+	IGD_SM_56MB = 0xFD,
+	IGD_SM_60MB = 0xFE,
+};
+
+enum igd_aperture_size {
+	IGD_AP_SZ_128MB = 0x00,
+	IGD_AP_SZ_256MB = 0x01,
+	IGD_AP_SZ_512MB = 0x02,
+};
+
 struct soc_intel_jasperlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 5a06e12347..daa6754989 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -6,6 +6,7 @@
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pcie_rp.h>
+#include <option.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
@@ -18,12 +19,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 {
 	unsigned int i;
 
-	/*
-	 * If IGD is enabled, set IGD stolen size to 60MB.
-	 * Otherwise, skip IGD init in FSP.
-	 */
 	m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
-	m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
+
+	if (m_cfg->InternalGfx) {
+		/* IGD is enabled, set IGD stolen size to 60MB. */
+		m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
+		m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
+	} else {
+		/* IGD is disabled, skip IGD init in FSP. */
+		m_cfg->IgdDvmt50PreAlloc = 0;
+	}
 
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->SaGv = config->SaGv;