UPSTREAM: soc/apollolake/pmc: Store the ACPI bar during set_resources stage

Because the resource for the ACPI BAR is fixed, pci_dev_set_resources
does not store it to the device. This means we need to do part of the
dance to get the ACPI IO region to work after coreboot.

Of course, this BAR can be destroyed later by the OS probing it, but
at least we try to get it working out of coreboot.

Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6
Original-Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15048
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit a942bd4952)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350087
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

src/soc/intel/apollolake/pmc.c

@@ -38,9 +38,29 @@ static void read_resources(device_t dev)
 	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
+/*
+ * Part 2:
+ * Resources are assigned, and no other device was given an IO resource to
+ * overlap with our ACPI BAR. But because the resource is FIXED,
+ * pci_dev_set_resources() will not store it for us. We need to do that
+ * explicitly.
+ */
+static void set_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_4);
+	pci_write_config32(dev, res->index, res->base);
+	dev->command |= PCI_COMMAND_IO;
+	res->flags |= IORESOURCE_STORED;
+	report_resource_stored(dev, res, " ACPI BAR");
+}
+
 static const struct device_operations device_ops = {
 	.read_resources		= read_resources,
-	.set_resources		= pci_dev_set_resources,
+	.set_resources		= set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 };