From 93adc63123341946dc7939e34612b148aac0034d Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 6 Mar 2017 07:00:57 -0500 Subject: [PATCH] UPSTREAM: mainboard/google/snappy: Override USB2 phy setting Fine tune USB2, need to override the following registers. port#1: PERPORTPETXISET=7 PERPORTTXISET=0 BUG=b:35858164 BRANCH=reef TEST=built, measured eye diagram on snappy, and reviewed by intel Change-Id: Ic4964e78338cb6d00d8d2dd61d627870ad656882 Signed-off-by: Patrick Georgi Original-Commit-Id: e4c85c128a5056e3f1ca7692edec97b33437da13 Original-Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f Original-Signed-off-by: Wisley Chen Original-Reviewed-on: https://review.coreboot.org/18590 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/451617 --- src/mainboard/google/reef/variants/snappy/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 6d1c9ef145..2b47c5727d 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -112,6 +112,12 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" + # Override USB2 PER PORT register (PORT 1) + register "usb2eye[1]" = "{ + .Usb20PerPortPeTxiSet = 7, + .Usb20PerPortTxiSet = 0, + }" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF