From 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Mon Sep 17 00:00:00 2001 From: ZhengShunQian Date: Fri, 28 Oct 2016 16:16:04 +0800 Subject: [PATCH] veyron: change .ddrconfig from 14 to 3 There are two configs sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc use .ddrconfig = 14 now. Changing .ddrconfig from 14 to 3 could help improving performance especially when accessing to contiguous memory. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits Because with .ddrconfig = 3, there are multi banks switching and saving DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Signed-off-by: ZhengShunQian Reviewed-on: https://chromium-review.googlesource.com/404691 Commit-Ready: Shunqian Zheng Tested-by: Shunqian Zheng Reviewed-by: Julius Werner --- .../google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- .../google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- .../google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- .../google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- .../google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549161..1c35c90047 100644 --- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01ab7..c4ce972bd0 100644 --- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549161..1c35c90047 100644 --- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01ab7..c4ce972bd0 100644 --- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549161..1c35c90047 100644 --- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01ab7..c4ce972bd0 100644 --- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549161..1c35c90047 100644 --- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01ab7..c4ce972bd0 100644 --- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 857365293b..8ad3338775 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -70,7 +70,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01ab7..c4ce972bd0 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549161..1c35c90047 100644 --- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01ab7..c4ce972bd0 100644 --- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2,