diff --git a/mainboard/amd/Kconfig b/mainboard/amd/Kconfig
index 856b75c78c..e2224b108b 100644
--- a/mainboard/amd/Kconfig
+++ b/mainboard/amd/Kconfig
@@ -35,6 +35,19 @@ config BOARD_AMD_DB800
 	help
 	  AMD DB800 Geode LX development board.
 
+config BOARD_AMD_DBM690T
+	bool "dbm690t"
+	select ARCH_X86
+	select OPTION_TABLE
+	select CPU_AMD_K8
+	select NORTHBRIDGE_AMD_K8
+	select SOUTHBRIDGE_AMD_SB600
+	select SOUTHBRIDGE_AMD_RS690
+	select SUPERIO_ITE_IT8712F
+	select IOAPIC
+	help
+	  AMD dbm690t development board.
+
 config BOARD_AMD_NORWICH
 	bool "Norwich"
 	select ARCH_X86
@@ -65,6 +78,11 @@ config MAINBOARD_DIR
 	default amd/db800
 	depends BOARD_AMD_DB800
 
+config MAINBOARD_DIR
+	string
+	default amd/dbm690t
+	depends BOARD_AMD_DBM690T
+
 config MAINBOARD_DIR
 	string
 	default amd/norwich
@@ -74,4 +92,3 @@ config MAINBOARD_DIR
 	string
 	default amd/serengeti
 	depends BOARD_AMD_SERENGETI
-
diff --git a/mainboard/amd/serengeti/Makefile b/mainboard/amd/serengeti/Makefile
index 69b38fe6fc..79462668ff 100644
--- a/mainboard/amd/serengeti/Makefile
+++ b/mainboard/amd/serengeti/Makefile
@@ -24,18 +24,19 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
 			$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
 			$(src)/arch/x86/stage1_mtrr.c \
+			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
+			$(src)/arch/x86/amd/model_fxx/stage1.c \
+			$(src)/northbridge/amd/k8/get_nodes.c \
+			$(src)/northbridge/amd/k8/libstage1.c \
 			$(src)/southbridge/amd/amd8111/stage1_smbus.c \
 			$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
 			$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
-			$(src)/arch/x86/amd/model_fxx/dualcore_id.c \
-			$(src)/arch/x86/amd/model_fxx/stage1.c \
-			$(src)/northbridge/amd/k8/coherent_ht.c \
-			$(src)/northbridge/amd/k8/libstage1.c \
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
 			$(src)/northbridge/amd/k8/reset_test.c \
+			$(src)/northbridge/amd/k8/coherent_ht.c \
 			$(src)/northbridge/amd/k8/incoherent_ht.c \
 			$(src)/arch/x86/pci_ops_conf1.c \
 			$(src)/arch/x86/stage1_mtrr.c \
diff --git a/mainboard/amd/serengeti/initram.c b/mainboard/amd/serengeti/initram.c
index 621614bcd9..991e863f00 100644
--- a/mainboard/amd/serengeti/initram.c
+++ b/mainboard/amd/serengeti/initram.c
@@ -249,9 +249,6 @@ int main(void)
 	dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 #endif
 
-#warning re-implement post_cache_as_ram
-	//       post_cache_as_ram(); // bsp switch stack to ram and copy sysinfo ram now
-
 	printk(BIOS_DEBUG, "stage1 returns\n");
 	return 0;
 }