From 934e5e0403deba59983a6fb05b85ea9b64714654 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 17 Oct 2000 13:18:43 +0000 Subject: [PATCH] reorg --- src/cpu/p6/earlymtrr.inc | 80 +++++ src/cpu/p6/microcode.c | 325 +++++++++++++++++++++ src/cpu/p6/mtrr.c | 180 ++++++++++++ src/northbridge/via/vt8601/raminit.inc | 171 +++++++++++ src/southbridge/via/vt82c686/southbridge.c | 122 ++++++++ 5 files changed, 878 insertions(+) create mode 100644 src/cpu/p6/earlymtrr.inc create mode 100644 src/cpu/p6/microcode.c create mode 100644 src/cpu/p6/mtrr.c create mode 100644 src/northbridge/via/vt8601/raminit.inc create mode 100644 src/southbridge/via/vt82c686/southbridge.c diff --git a/src/cpu/p6/earlymtrr.inc b/src/cpu/p6/earlymtrr.inc new file mode 100644 index 0000000000..704efae622 --- /dev/null +++ b/src/cpu/p6/earlymtrr.inc @@ -0,0 +1,80 @@ +// This is very early MTRR code so that DRAM runs at reasonable speeds. +// we do a better job of exact MTRR setup later +#if 1 + /* enable caching for all using variable mtrr */ + + mov $0x200, %ecx + rdmsr + and $0xfffffff0, %edx + or $0x00000000, %edx + and $0x00000f00, %eax + or $0x00000006, %eax + wrmsr + + mov $0x201, %ecx + rdmsr + and $0xfffffff0, %edx + or $0x0000000f, %edx + and $0x000007ff, %eax + or $0xf0000800, %eax + wrmsr +#endif +#if 0 + /* enable read only caching for top 64K of flash using variable mtrr */ + + mov $0x200, %ecx + rdmsr + and $0xfffffff0, %edx + or $0x00000000, %edx + and $0x00000f00, %eax + or $0x000f0006, %eax + wrmsr + + mov $0x201, %ecx + rdmsr + and $0xfffffff0, %edx + or $0x0000000f, %edx + and $0x000007ff, %eax + or $0xffff0800, %eax + wrmsr +#endif +#if 0 + /* enable read only caching for top 64K of flash using fixed mtrr */ + /* + * This seems to enable caching for entire 1st meg. Maybe + * all the other fixed ones don't have the default I was + * assuming. + */ + mov $0x26e, %ecx + rdmsr + mov $0x05050505, %edx + mov $0x05050505, %eax + wrmsr + + mov $0x26f, %ecx + rdmsr + mov $0x05050505, %edx + mov $0x05050505, %eax + wrmsr +#endif + /* + * Set the default memory type and enable + * fixed and variable MTRRs. + */ + + mov $0x2ff, %ecx + rdmsr + and $0xfffff300, %eax +#if 1 /* Enable/Disable MTRRs */ + or $0x00000800, %eax +#endif +#if 0 /* Enable fixed MTRRs if MTRRs are enabled */ + or $0x00000400, %eax +#endif + wrmsr + + /* enable cache */ + + mov %cr0, %eax + and $0x9fffffff,%eax + mov %eax, %cr0 diff --git a/src/cpu/p6/microcode.c b/src/cpu/p6/microcode.c new file mode 100644 index 0000000000..a15217be86 --- /dev/null +++ b/src/cpu/p6/microcode.c @@ -0,0 +1,325 @@ +#include +#include +#include +#include +#include + +struct microcode { + unsigned int hdrver; + unsigned int rev; + unsigned int date; + unsigned int sig; + + unsigned int cksum; + unsigned int ldrver; + unsigned int pf; + + unsigned int reserved[5]; + unsigned int bits[500]; +}; + +unsigned int microcode_updates [] = { + /* + Copyright Intel Corporation, 1995, 96, 97, 98, 99, 2000. + + These microcode updates are distributed for the sole purpose of + installation in the BIOS or Operating System of computer systems + which include an Intel P6 family microprocessor sold or distributed + to or by you. You are authorized to copy and install this material + on such systems. You are not authorized to use this material for + any other purpose. + */ + +/* MU16830c.inc */ + 0x00000001, 0x0000000c, 0x01102000, 0x00000683, + 0xb1605bca, 0x00000001, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x7d021266, 0xd3890df1, 0x08a3a61b, 0x3c9bd396, + 0x516b77d0, 0xf119ce39, 0xd63a44b0, 0x523efada, + 0x1a0c3ed7, 0x04711f21, 0x515f945e, 0xbb5f13ba, + 0x254eabfc, 0x5bd1e959, 0x67373898, 0x61605a8f, + 0x6ea7c5a9, 0x5e64a058, 0xc0a019ee, 0x56af4cfe, + 0x1acd6406, 0x4e7eb040, 0xf2ebd7ef, 0xc659db4f, + 0xfe77108b, 0xfdceb47b, 0xf0757eb8, 0xb1622949, + 0xdceb744b, 0x19e2ad26, 0xe9c745ab, 0xb385f196, + 0x9ecc3483, 0x0a126045, 0x5320d6be, 0x8557a583, + 0x7faf0073, 0x5ab281b4, 0x34dbbac6, 0x8a0bc7cd, + 0x52584248, 0x3c3ef309, 0x41403737, 0x8200991d, + 0x7e0dfb86, 0xea1e3a8f, 0x5b87ca8a, 0x004be481, + 0x74e9fd6f, 0x80d518d6, 0xf10672c8, 0x2b8936b5, + 0xd7092242, 0xbaa950a4, 0xaa6a2305, 0xeccbb48b, + 0x43f6b561, 0x8607570a, 0x6143ba7b, 0x4c534447, + 0x45d97f76, 0x0ccf7b83, 0xd89482bd, 0x32c46a60, + 0x6db7b842, 0x0f7ad008, 0x4ce4968c, 0x2af52761, + 0x26a2a653, 0x5806f996, 0xfe844901, 0x6164e754, + 0xaf9287ab, 0x1f495a8d, 0x6cd70b5e, 0x681df673, + 0xc94dc88f, 0x4b9650f8, 0xdfc826d9, 0xb5710e59, + 0x80ed0f08, 0x615ce9c2, 0x0864130d, 0xc604520e, + 0x9be149db, 0xeefb463f, 0x15b7e000, 0xc3bf13ab, + 0x29d75556, 0x99420678, 0x505b5858, 0x6dadaeae, + 0xf87f8f56, 0xe9be5867, 0xd772475a, 0x0a4642c0, + 0xc59b2b86, 0x9e0f0a7f, 0x4c54834f, 0xb39f1d7c, + 0xd52dac56, 0x1fdde74b, 0x60fddc1c, 0x367321f1, + 0x98a7c9bd, 0x9a7896d2, 0x8d1f200b, 0x7975e907, + 0x0e7d4411, 0x1671c027, 0x438550a2, 0x385dfc21, + 0xb26c638d, 0x9b43b0d2, 0x03a0512d, 0x6b195c14, + 0x9db53322, 0x78512b73, 0x86714a5b, 0x9b900bb3, + 0xdbd702f9, 0xcdb985cb, 0x1033fd1e, 0xc75ed099, + 0x8a8c99fc, 0x12c5b949, 0x913249a0, 0xbd40f4b1, + 0x87406189, 0x977927e0, 0x76915a37, 0x79ffa5f2, + 0x5e1812b8, 0x8e7eb819, 0x6bfc46a5, 0x8d80c798, + 0x56d5a7ec, 0x5904350a, 0x82a1b59a, 0x27c64a52, + 0x4effaac0, 0x8e1519ec, 0x29ffed29, 0x3eaccc55, + 0x823e79c1, 0xdb5f2295, 0xb6ab9c23, 0xb301f2c5, + 0xe17f14f3, 0xf4e8892a, 0x107c9db8, 0x6a8a8ff4, + 0xaf9df422, 0xb14bd8f4, 0x00fa2a4c, 0x15324701, + 0x95e86a3b, 0xf74566e1, 0x386a788f, 0x9333e875, + 0xdea61190, 0x307a5338, 0xd9cec152, 0xe77165da, + 0x54187a14, 0x9a7d99bf, 0x4b31e986, 0x7d7ed557, + 0x626bb548, 0x434c4a78, 0x562b1588, 0xe0d15f63, + 0x524473f7, 0x484459e1, 0xbe617125, 0xb96f7eb8, + 0xb86620f7, 0xcc1e09b1, 0x7ad3b154, 0xae1f697e, + 0x11d0bfb1, 0xb1218568, 0x83a44b34, 0xeecec8bc, + 0xa06b01d8, 0xccadf143, 0xe1f9702c, 0x1e7c3d0d, + 0xd907d836, 0x780b3a02, 0x9a5e81fa, 0x0015cf61, + 0xbd148c0c, 0x84a65389, 0x99e77502, 0x0d630a94, + 0xd7f97779, 0x75567907, 0xa859be05, 0x8baab7b7, + 0x4f1a8101, 0x9992f951, 0xdd918c8a, 0x12b3ca17, + 0x117358b4, 0xf27a4783, 0xe3363be6, 0x3847f05d, + 0xb642595a, 0x4fbb98ae, 0xd6259c55, 0x3c72ff94, + 0xa9c3e102, 0x256e26c1, 0x2faf190b, 0xaaa1d198, + 0x8e25fc06, 0x8aa6fc5d, 0x9b994d46, 0x15045f23, + 0x23813558, 0x0173ef1b, 0xe4198a76, 0x36aa0de4, + 0x341d7595, 0xe186740f, 0xec371375, 0x1a4cabbe, + 0x6241897f, 0x388bd888, 0x2542e1f7, 0x61620df5, + 0x209f9d94, 0xca90f89b, 0x286a3e92, 0xea1cc30f, + 0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631, + 0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a, + 0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f, + 0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038, + 0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c, + 0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea, + 0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7, + 0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed, + 0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce, + 0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1, + 0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643, + 0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2, + 0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95, + 0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708, + 0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550, + 0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e, + 0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300, + 0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06, + 0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226, + 0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff, + 0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f, + 0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa, + 0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900, + 0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282, + 0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5, + 0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21, + 0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f, + 0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b, + 0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a, + 0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb, + 0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1, + 0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8, + 0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18, + 0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d, + 0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429, + 0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b, + 0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879, + 0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950, + 0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95, + 0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61, + 0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff, + 0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9, + 0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44, + 0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d, + 0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8, + 0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5, + 0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276, + 0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d, + 0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777, + 0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758, + 0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f, + 0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60, + 0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb, + 0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef, + 0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d, + 0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89, + 0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81, + 0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8, + 0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0, + 0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007, + 0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c, + 0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6, + 0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75, + 0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116, + 0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e, + 0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, +/* MU16810d.inc */ + 0x00000001, 0x0000000d, 0x09211999, 0x00000681, + 0x31708166, 0x00000001, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x710e5240, 0xab8bc2df, 0x6e652d5a, 0xcc16718b, + 0xaa5c7d1a, 0x43ac1ba0, 0xbdf8684e, 0x82565fa7, + 0x1d108edc, 0x96d2d5a2, 0x85f783a0, 0x16e4cba1, + 0xbc311213, 0xc36c45a2, 0x443b8d2b, 0xfdc5e9ce, + 0xbb6f8637, 0x47011b8b, 0xf3898e4a, 0xb3e90f68, + 0x60af6e3a, 0xff9d3de4, 0x9fb2333c, 0x5a1a39ce, + 0xffd75d72, 0xa60cc2c0, 0x5729267c, 0xfc6d2da7, + 0x8a2c8ae7, 0x71aba5ba, 0xb639ff31, 0x8d1642b8, + 0x3aa67efc, 0x9f786473, 0xaedec560, 0x1acb694f, + 0x97582a6f, 0x8dc17ea5, 0x19636cfe, 0xb5032243, + 0xc46f764f, 0x3a5d3833, 0xf3d1a2b9, 0xc22e59be, + 0x15e0b2f3, 0xe58eff24, 0xc679600d, 0x21a3a845, + 0xc11cc921, 0xed2f5061, 0x2d4db0d1, 0xcc0cc78f, + 0x80197c08, 0x20739d8a, 0xc92ec866, 0xacef343b, + 0x47c0913a, 0xee8a69e4, 0xa7b0157e, 0x4c3607a9, + 0xcc7ff7ea, 0xb0a36667, 0x41d1bcf0, 0xf54c42d2, + 0x946c590e, 0x6da18fe9, 0xf20df0e6, 0x984a2160, + 0x479becd3, 0xfb11dd36, 0xbb816653, 0x60c605c2, + 0xf52efe8b, 0x90a9f863, 0x69654bfa, 0xf0f03f7c, + 0xbf0498d5, 0x68708d82, 0xdab94924, 0x92371217, + 0x603feed7, 0xf0ff8329, 0x9c8769df, 0x6d40ab73, + 0xd8fd132a, 0x9335543f, 0x40fd3abb, 0xf25665a0, + 0x93fe56a6, 0x682a3b24, 0xf3a0f14a, 0x97e92084, + 0x4e8736a3, 0xf322db48, 0xb65de2ad, 0x6af68474, + 0xfd6dae0d, 0x953afb0e, 0x6ef22a82, 0xfa7a3d7b, + 0xb5fe683f, 0x647579c3, 0xd184e7db, 0x99ec7c97, + 0x66486a26, 0xf08c8290, 0x94eb3fce, 0x6305e16e, + 0xd61dd210, 0x9b8bdbba, 0x41a4b4f5, 0xfca38a75, + 0x9c55c7a4, 0x6a4b1f02, 0xf277077a, 0x900e3d03, + 0x4f173146, 0xf6fbf7c8, 0xb2636cb2, 0x6329a9d7, + 0xf2697eb4, 0x90f80f6f, 0x65de6167, 0xfc6cd065, + 0xb4326188, 0x67507c3a, 0xdf3179ff, 0x91207c0b, + 0x6408ad58, 0xf7e7d2fe, 0x999af7c0, 0x6a994828, + 0xdaecedf4, 0x93cba457, 0x4d924b31, 0xf12b5ae1, + 0x9563d541, 0x65bd28f8, 0xfa87a363, 0x983adc3d, + 0x45c4f64d, 0xfae3e1ef, 0xb2eb287f, 0x6050f699, + 0xfb28cfb6, 0x999b1d45, 0x65027980, 0xf4e507d0, + 0xbbd059b7, 0x64cb2688, 0xd29dff15, 0x90927c2c, + 0x6d52471a, 0xf64fc745, 0x9e4050ff, 0x68b66e3f, + 0xd0a1dd96, 0x9fe8a5a3, 0x454c936b, 0xf926115d, + 0x9bfb60ff, 0x604049aa, 0xf3509e5c, 0x9d6cf26f, + 0x4d777c5a, 0xfd7cd5ff, 0xb15d4f35, 0x6b1aa6e3, + 0xfa279f20, 0x94916fae, 0x9b04dbcc, 0x600defd9, + 0xf2977cd8, 0x65fa64be, 0x968feaee, 0xc11681af, + 0x66568af6, 0xa539a4ee, 0xcfed5cb1, 0x108445de, + 0xa603dfdd, 0xbf5ada02, 0x14b868c5, 0xb2d3b8d2, + 0xbabf3637, 0x0c25bfbc, 0xb7a4c247, 0xf2837e05, + 0x062ce963, 0xfcb65c46, 0xc6d190e7, 0x4dfce123, + 0xcb0bf4c7, 0x8bff9d9d, 0x6794e002, 0x2879661e, + 0xa5e93199, 0x77be4be8, 0x22fe3324, 0xb943e4ef, + 0x73463d52, 0x31471050, 0xb68fd63f, 0x84cad24f, + 0x343d922b, 0x42b9ab31, 0x88ee1549, 0xe913e2ab, + 0x4a127048, 0x5057f79f, 0x636eb512, 0x42e02f9c, + 0xd3a8b863, 0x9bc40609, 0x4a18edb5, 0x86a4bdaa, + 0x91819a4b, 0x12a11e17, 0x8a6d7f21, 0xf42998d9, + 0x132b6bbd, 0xe3239feb, 0xf52519d7, 0xada08128, + 0xe6febacf, 0x44e15a80, 0xa977610a, 0xf56a8665, + 0x4693b6f0, 0xb8386320, 0xfcf7d071, 0xb8a1128d, + 0xb2a45d18, 0x075a2095, 0x98ebde53, 0xe8762eaf, + 0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631, + 0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a, + 0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f, + 0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038, + 0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c, + 0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea, + 0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7, + 0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed, + 0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce, + 0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1, + 0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643, + 0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2, + 0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95, + 0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708, + 0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550, + 0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e, + 0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300, + 0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06, + 0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226, + 0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff, + 0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f, + 0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa, + 0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900, + 0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282, + 0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5, + 0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21, + 0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f, + 0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b, + 0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a, + 0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb, + 0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1, + 0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8, + 0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18, + 0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d, + 0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429, + 0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b, + 0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879, + 0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950, + 0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95, + 0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61, + 0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff, + 0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9, + 0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44, + 0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d, + 0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8, + 0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5, + 0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276, + 0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d, + 0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777, + 0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758, + 0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f, + 0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60, + 0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb, + 0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef, + 0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d, + 0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89, + 0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81, + 0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8, + 0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0, + 0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007, + 0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c, + 0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6, + 0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75, + 0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116, + 0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e, + 0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, +}; + +void intel_display_cpuid_microcode(void) +{ + unsigned int eax, ebx, ecx, edx; + unsigned int pf, rev, sig, val[2]; + unsigned int x86_model, i; + struct microcode *m; + + /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ + wrmsr(0x8B, 0, 0); + intel_cpuid(1, &eax, &ebx, &ecx, &edx); + rdmsr(0x8B, val[0], rev); + x86_model = (eax >>4) & 0x0f; + sig = eax; + + pf = 0; + if (x86_model >= 5) { + rdmsr(0x17, val[0], val[1]); + pf = 1 << ((val[1] >> 18) & 7); + } + printk(KERN_INFO "microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n", + sig, pf, rev); + + m = (void *)µcode_updates; + for(i = 0; i < sizeof(microcode_updates)/sizeof(struct microcode); i++) { + if ((m[i].sig == sig) && (m[i].pf == pf)) { + wrmsr(0x79, (unsigned int)&m[i].bits, 0); + __asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx"); + rdmsr(0x8B, val[0], val[1]); + printk(KERN_INFO "microcode updated from revision %d to %d\n", + rev, val[1]); + } + } +} diff --git a/src/cpu/p6/mtrr.c b/src/cpu/p6/mtrr.c new file mode 100644 index 0000000000..0376adc07f --- /dev/null +++ b/src/cpu/p6/mtrr.c @@ -0,0 +1,180 @@ +/* + * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6 + * + * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel + * + * Copyright 2000 Silicon Integrated System Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming + * + * $Id$ + */ + +#include +#include + +#define arraysize(x) (sizeof(x)/sizeof((x)[0])) + +static unsigned int mtrr_msr[] = { + MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, + MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, + MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, +}; + +static unsigned char fixed_mtrr_values[][4] = { + /* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */ + {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, + {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, + + /* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */ + {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, + {MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK}, + + /* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */ + {MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB}, + {MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB}, + + /* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + + /* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */ + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, + {MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH}, +}; + +void +intel_enable_fixed_mtrr() +{ + unsigned long low, high; + + rdmsr(MTRRdefType_MSR, low, high); + low |= 0xc00; + wrmsr(MTRRdefType_MSR, low, high); +} + +void +intel_enable_var_mtrr() +{ + unsigned long low, high; + + rdmsr(MTRRdefType_MSR, low, high); + low |= 0x800; + wrmsr(MTRRdefType_MSR, low, high); +} + +/* setting fixed mtrr, you can do some experiments with different memory type + defined in the table "fixed_mtrr_values" */ +void intel_set_fixed_mtrr() +{ + unsigned int i; + unsigned long low, high; + + for (i = 0; i < arraysize(mtrr_msr); i++) { + low = *(unsigned long *) fixed_mtrr_values[i*2]; + high = *(unsigned long *) fixed_mtrr_values[i*2+1]; + wrmsr(mtrr_msr[i], low, high); + } + +} + +/* setting variable mtrr, comes from linux kernel source */ +void intel_set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type) +{ + + + if (reg >= 8) + return; + + if (size == 0) { + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR (reg), 0, 0); + } else { + wrmsr (MTRRphysBase_MSR (reg), base | type, 0); + wrmsr (MTRRphysMask_MSR (reg), ~(size - 1) | 0x800, 0); + } +} + +/* some secret MSR registers make 5x performance boost, + hardcoded for 128MB SDRAM on Celeron and PII */ +void intel_l2_cache_on() +{ + unsigned long low, high; + + low = 0x134052b; + high = 0x00; + wrmsr(0x11e, low, high); +} + +/* setting up variable and fixed mtrr + ToDo: 1. still need to find out how to set size and alignment correctly + 2. should we invalid cache by INVLD or WBINVD ?? */ +#ifdef INTEL_PPRO_MTRR +#ifdef ENABLE_FIXED_AND_VARIABLE_MTRRS +void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) +{ +#ifdef SIS630 + /* hardcoded for 128MB SDRAM, 4 MB SMA */ + intel_set_var_mtrr(0, 0, 128 * 1024 * 1024, MTRR_TYPE_WRBACK); + intel_set_var_mtrr(1, 124 * 1024 * 1024, 4 * 1024 * 1024, MTRR_TYPE_UNCACHABLE); +#else + printk("Setting variable MTRR 0 to %dK\n", ramsizeK); + intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK); +#endif + intel_set_fixed_mtrr(); + + /* enable fixed MTRR */ + intel_enable_fixed_mtrr(); + intel_enable_var_mtrr(); + + //intel_l2_cache_on(); +} +#else /* ENABLE_FIXED_AND_VARIABLE_MTRRS */ +void intel_set_mtrr(unsigned long rambase, unsigned long ramsizeK) +{ + intel_set_var_mtrr(0, 0, ramsizeK * 1024, MTRR_TYPE_WRBACK); + intel_enable_var_mtrr(); +// intel_set_fixed_mtrr(); +} +#endif /* ENABLE_FIXED_AND_VARIABLE_MTRRS */ +#endif /* INTEL_PPRO_MTRR */ diff --git a/src/northbridge/via/vt8601/raminit.inc b/src/northbridge/via/vt8601/raminit.inc new file mode 100644 index 0000000000..4191578061 --- /dev/null +++ b/src/northbridge/via/vt8601/raminit.inc @@ -0,0 +1,171 @@ +/* +This software and ancillary information (herein called SOFTWARE ) +called LinuxBIOS is made available under the terms described +here. The SOFTWARE has been approved for release with associated +LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has +been authored by an employee or employees of the University of +California, operator of the Los Alamos National Laboratory under +Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The +U.S. Government has rights to use, reproduce, and distribute this +SOFTWARE. The public may copy, distribute, prepare derivative works +and publicly display this SOFTWARE without charge, provided that this +Notice and any statement of authorship are reproduced on all copies. +Neither the Government nor the University makes any warranty, express +or implied, or assumes any liability or responsibility for the use of +this SOFTWARE. If SOFTWARE is modified to produce derivative works, +such modified SOFTWARE should be clearly marked, so as not to confuse +it with the version available from LANL. + */ +/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL + * rminnich@lanl.gov + */ + +#define loop200 $0x5000 +#define loop100 $0x2500 + +/*; new code... pulled from via stuff.*/ +/* initialize registers */ + // memory clk enable. We are not using ECC + CS_WRITE($0x78, $0x01) + // dram control, see the book. + CS_WRITE($0x68, $0x00) + // dram control, see the book. + CS_WRITE($0x6B, $0x00) + // 64/128 MB dram + CS_WRITE($0x58, $0x88) + // 64/128 MB dram + CS_WRITE($0x59, $0x88) + // bank 0 ends at 64 MB + CS_WRITE($0x5A, $0x08) + // bank 1 ends at 64 MB + CS_WRITE($0x5B, $0x10) + // bank 2 ends at 64 MB + CS_WRITE($0x5C, $0x10) + // bank 2 ends at 64 MB + CS_WRITE($0x5D, $0x10) + // bank 2 ends at 64 MB + CS_WRITE($0x5E, $0x10) + // bank 2 ends at 64 MB + CS_WRITE($0x5F, $0x10) + + // SDRAM in all banks + CS_WRITE($0x60, $0xFF) + // DRAM timing. I'm suspicious of this + // This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5. + // ras precharge 4T, RAS pulse 5T, CAS 2T + // as per the note below, we change to cas 3 2000/8/31 + // cas2 is 0xd6, cas3 is 0xe6 + // we're also backing off write pulse width to 2T, so result is 0xee + CS_WRITE($0x64, $0xee) + CS_WRITE($0x65, $0xee) + CS_WRITE($0x66, $0xee) + + // dram frequency select. We set 66/66. + // no 256 m, enable 4K pages for 64M dram. + CS_WRITE($0x69, $0x04) + // refresh counter, disabled. + CS_WRITE($0x6A, $0x00) + // clkenable configuration. Not sure this is right! + CS_WRITE($0x6C, $0x00) + // dram read latch delay of 1 ns, MD drive 8 mA, + // high drive strength on MA[2: 13], we#, cas#, ras# + // As per Cindy Lee, set to 0x37, not 0x57 + CS_WRITE($0x6D, $0x37) + +/* begin to initialize*/ + // I forget why we need this, but we do + mov $0xa55a5aa5, %eax + mov %eax, 0 + mov %eax, 0x4000000 + +/* set NOP*/ + CS_WRITE($0x6C, $0x01) + + +/* wait 200us*/ + // You need to do the memory reference. That causes the nop cycle. + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop200) + + +/* set precharge */ + CS_WRITE($0x6C, $0x02) + +/* dummy reads*/ + mov 0x0, %eax + mov 0x4000000, %eax + +/* set CBR*/ + CS_WRITE($0x6C, $0x04) + +/* do 8 reads and wait 100us between each - from via*/ + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + mov 0x0, %eax + mov 0x4000000, %eax + DELAY(loop100) + +/* set MRS*/ + // 0x150 is cas2. We are now using 0x1d0, which is cas3 + CS_WRITE($0x6c, $0x03) + movl $0x1d0, %ecx + movl (%ecx), %eax + movl $0x40001d0, %ecx + movl (%ecx), %eax + +/* set to normal mode */ + CS_WRITE($0x6C, $0x00) + movl $0x55aa55aa, %eax + mov %eax, 0x0 + mov 0x0, %eax + + // Set the refresh rate. + CS_WRITE($0x6A, $0x65) + // enable multi-page open + CS_WRITE($0x6B, $0x01) + + +/* From Mike Fan: + Hi all: + If you are porting PM133, then you have to set DRAM Row Ending Address. + You did not set Rx56 and Rx57 in intel_pm133ram.S. + That register setting is like Rx5A~Rx5F. + Maybe could fix the mem wrapping issue. + (from Ron Minnich) + My manual says these are non-cacheable region registers. + (Turns out the manual is wrong. However, this did not help. + 2000/8/31 8:49 am I am setting all dram to cas3, and if that fails, + I'll be trying some of Cindy's other recommendations. + DRAM is currently CAS2. Symptom is an explosion in free_all_bootmem_core, + In the loop where it is freeing bootmem alloc pages from low mem. + 2000/8/31: 10:57 No change, Linux still crashes. We'll try Cindy Lee's recommendation + RE Register 0x6d, set it to 0x37. All our other settings conform to her + other recommendations. We also need to see whether we should be setting + Fixed MTRRs, but that seems unlikely. + 2000/8/31: 5:56 PM. No significant change. We're going to try to use 1 cycle writes + instead of 2. None of this feels like it is the real problem. Fixed MTRRs + helped a tiny bit. We can get to schedule() before we crash, but only + if we set a breakpoint after the first loop in free_all_bootmem_core + */ + CS_WRITE($0x56, $0x10) + CS_WRITE($0x57, $0x10) diff --git a/src/southbridge/via/vt82c686/southbridge.c b/src/southbridge/via/vt82c686/southbridge.c new file mode 100644 index 0000000000..1ffc29f7f3 --- /dev/null +++ b/src/southbridge/via/vt82c686/southbridge.c @@ -0,0 +1,122 @@ +#include +#include +#include + +void keyboard_on() +{ + volatile unsigned char regval; + + /* regval = intel_conf_readb(0x8000385A); */ + /*regval |= 0x01; */ + regval = 0xff; + intel_conf_writeb(0x8000385A, regval); + + /* disable USB1 */ + intel_conf_writeb(0x80003A3C, 0x00); + intel_conf_writeb(0x80003A04, 0x00); + regval = intel_conf_readb(0x80003848); + regval |= 0x04; + intel_conf_writeb(0x80003848, regval); + + /* disable USB2 */ + intel_conf_writeb(0x80003B3C, 0x00); + intel_conf_writeb(0x80003B04, 0x00); + regval = intel_conf_readb(0x80003885); + regval |= 0x10; + intel_conf_writeb(0x80003885, regval); + + pc_keyboard_init(); + +} + +void nvram_on() +{ + /* the VIA 686A South has a very different nvram setup than the piix4e ... */ + /* turn on ProMedia nvram. */ + /* TO DO: use the PciWriteByte function here. */ + intel_conf_writeb(0x80003843, 0xFF); +} + +void southbridge_fixup() +{ + unsigned int devfn; + unsigned char enables; + + // enable the internal I/O decode + // to do: use the pcibios_find function here, instead of + // hard coding the devfn. + devfn = PCI_DEVFN(7, 0); + enables = pcibios_read_config_byte(0, devfn, 0x81, &enables); + enables |= 0x80; + pcibios_write_config_byte(0, devfn, 0x81, enables); + + // enable com1 and com2. + enables = pcibios_read_config_byte(0, devfn, 0x83, &enables); + // 0x80 is enable com port b, 0x1 is to make it com2, 0x8 is enable com port a as com1 + enables = 0x80 | 0x1 | 0x8 ; + pcibios_write_config_byte(0, devfn, 0x83, enables); + // note: this is also a redo of some port of assembly, but we want everything up. + // set com1 to 115 kbaud + // not clear how to do this yet. + // forget it; done in assembly. + // enable IDE, since Linux won't do it. + // First do some more things to devfn (7,0) + // note: this should already be cleared, according to the book. + pcibios_read_config_byte(0, devfn, 0x48, &enables); + printk("IDE enable in reg. 48 is 0x%x\n", enables); + enables &= ~2; // need manifest constant here! + printk("set IDE reg. 48 to 0x%x\n", enables); + pcibios_write_config_byte(0, devfn, 0x48, enables); + + // set default interrupt values (IDE) + pcibios_read_config_byte(0, devfn, 0x4a, &enables); + printk("IRQs in reg. 4a are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk("setting reg. 4a to 0x%x\n", enables); + pcibios_write_config_byte(0, devfn, 0x4a, enables); + + // set up the serial port interrupts. + // com2 to 3, com1 to 4 + pcibios_write_config_byte(0, devfn, 0x52, 0x34); + + devfn = PCI_DEVFN(7, 1); + pcibios_read_config_byte(0, devfn, 0x40, &enables); + printk("enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pcibios_write_config_byte(0, devfn, 0x40, enables); + pcibios_read_config_byte(0, devfn, 0x40, &enables); + printk("enables in reg 0x40 read back as 0x%x\n", enables); + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + pcibios_read_config_byte(0, devfn, 0x9, &enables); + printk("enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + pcibios_write_config_byte(0, devfn, 0x9, enables); + pcibios_read_config_byte(0, devfn, 0x9, &enables); + printk("enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + pcibios_read_config_byte(0, devfn, 0x4, &enables); + printk("command in reg 0x4 0x%x\n", enables); + enables |= 5; + pcibios_write_config_byte(0, devfn, 0x4, enables); + pcibios_read_config_byte(0, devfn, 0x4, &enables); + printk("command in reg 0x4 reads back as 0x%x\n", enables); + + // oh well, the PCI BARs don't work right. + // This chip will not work unless IDE runs at standard legacy + // values. + + pcibios_write_config_dword(0, devfn, 0x10, 0x1f1); + pcibios_write_config_dword(0, devfn, 0x14, 0x3f5); + pcibios_write_config_dword(0, devfn, 0x18, 0x171); + pcibios_write_config_dword(0, devfn, 0x1c, 0x375); + pcibios_write_config_dword(0, devfn, 0x20, 0xcc0); + + +}