diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index a30fc40465..24d72d45bb 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -17,258 +17,275 @@ #ifndef _TEGRA124_CLK_RST_H_ #define _TEGRA124_CLK_RST_H_ -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll { - u32 pll_base; /* the control register */ - /* pll_out[0] is output A control, pll_out[1] is output B control */ - u32 pll_out[2]; - u32 pll_misc; /* other misc things */ -}; - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll_simple { - u32 pll_base; /* the control register */ - u32 pll_misc; /* other misc things */ -}; - -struct clk_pllm { - u32 pllm_base; /* the control register */ - u32 pllm_out; /* output control */ - u32 pllm_misc1; /* misc1 */ - u32 pllm_misc2; /* misc2 */ -}; - -/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ -struct clk_set_clr { - u32 set; - u32 clr; -}; - -/* - * Most PLLs use the clk_pll structure, but some have a simpler two-member - * structure for which we use clk_pll_simple. The reason for this non- - * othogonal setup is not stated. - */ -enum { - TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ - TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ - TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ - TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ - TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ - TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ -}; - /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ struct __attribute__ ((__packed__)) clk_rst_ctlr { - u32 crc_rst_src; /* _RST_SOURCE_0,0x00 */ - u32 crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ - u32 crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ - u32 crc_reserved0; /* reserved_0, 0x1C */ - u32 crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - u32 crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - u32 crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - u32 crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - u32 crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - u32 crc_reserved01; /* reserved_0_1, 0x34 */ - u32 crc_reserved02; /* reserved_0_2, 0x38 */ - u32 crc_reserved1; /* reserved_1, 0x3C */ - u32 crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - u32 crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - u32 crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - u32 crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - u32 crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - u32 crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - u32 crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - u32 crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - u32 crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - - struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - - /* PLLs from 0xe0 to 0xf4 */ - struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - - u32 crc_reserved10; /* _reserved_10, 0xF8 */ - u32 crc_reserved11; /* _reserved_11, 0xFC */ - /* 0x100 0x1fc */ - u32 src_i2s1; - u32 src_i2s2; - u32 src_spdif_out; - u32 src_spdif_in; - u32 src_pwm; - u32 _pad1; - u32 src_sbc2; - u32 src_sbc3; - u32 _pad2[2]; - u32 src_i2c1; - u32 src_i2c5; - u32 _pad[1]; - u32 src_sbc1; - u32 src_disp1; - u32 src_disp2; - u32 _pad4[2]; - u32 src_vi; - u32 _pad5; - u32 src_sdmmc1; - u32 src_sdmmc2; - u32 src_g3d; - u32 src_g2d; - u32 src_ndflash; - u32 src_sdmmc4 ; - u32 src_vfir; - u32 src_epp; - u32 src_mpe; - u32 src_hsi; - u32 src_uarta; - u32 src_uartb; - u32 src_host1x; - u32 _pad6[2]; - u32 src_hdmi; - u32 _pad7[2]; - u32 src_i2c2; - u32 src_emc0; /* not correctly documented as to address. */ - u32 src_uartc; - u32 _pad71; - u32 src_vi_sensor; - u32 _pad8[2]; - u32 src_sbc4; - u32 src_i2c3; - u32 src_sdmmc3; - u32 src_uartd; - u32 src_uarte; - u32 src_vde; - u32 src_owr; - u32 src_nor; - u32 src_csite; - u32 src_i2s0; - u32 src_dtv; - u32 pad9[4]; - u32 src_msenc; - u32 src_tsec; - u32 pad10; - u32 src_osc; - - u32 crc_reserved20[32]; /* _reserved_20, 0x200-27c */ - - u32 crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - u32 crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - u32 crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - u32 crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - u32 crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - u32 crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - u32 crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ - - u32 crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - u32 crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ - struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; - - u32 crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ - - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ - struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; - - u32 crc_reserved31; /* _reserved_31, 0x338 */ - - u32 crc_ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ - - u32 crc_rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - u32 crc_rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - u32 crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - u32 crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - u32 crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ - - u32 crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ - u32 crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ - u32 crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - u32 crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - u32 crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - u32 crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - u32 crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - u32 crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - u32 crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - u32 crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - u32 crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - u32 crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - u32 crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ - struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - u32 crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450*/ - u32 crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454*/ - u32 crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458*/ - u32 crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C*/ - u32 crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - u32 crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - u32 crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - u32 crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - u32 crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - u32 crc_reserved40[1]; /* _reserved_40, 0x474 */ - u32 crc_intstatus; /* __INTSTATUS_0, 0x478 */ - u32 crc_intmask; /* __INTMASK_0, 0x47C */ - u32 crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - u32 crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - u32 crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - u32 crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ - u32 crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - u32 crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - u32 crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - u32 crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - u32 crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - u32 crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - u32 crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - u32 crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - u32 crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - u32 crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - - u32 crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - u32 crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - u32 crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - u32 crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - u32 crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - u32 crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - u32 crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - u32 crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - u32 crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - u32 crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - u32 crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - u32 crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ - u32 crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - u32 crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - u32 crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - u32 crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ - u32 crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - u32 crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - u32 crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - u32 crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ - u32 crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - u32 crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - u32 crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - u32 crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ - u32 crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - u32 crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - u32 crc_reserved51[1]; /* _reserved_51, 0x538 */ - u32 crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ - u32 crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - u32 crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - u32 crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - u32 crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ - u32 crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - u32 crc_reserved52[1]; /* _reserved_52, 0x554 */ - u32 crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - u32 crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - - /* T124 - skip to 0x600 here for new CLK_SOURCE_ regs */ - u32 crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ - u32 crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ + u32 rst_src; /* _RST_SOURCE, 0x000 */ + u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ + u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ + u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ + u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ + u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ + u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ + u32 _rsv0; /* 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ + u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ + u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ + u32 _rsv1[3]; /* 0x034-03c */ + u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ + u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ + u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ + u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ + u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ + u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ + u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ + u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ + u32 _rsv2[8]; /* 0x060-07C */ + u32 pllc_base; /* _PLLC_BASE, 0x080 */ + u32 pllc_out; /* _PLLC_OUT, 0x084 */ + u32 plcc_misc2; /* _PLLC_MISC2, 0x088 */ + u32 plcc_misc; /* _PLLC_MISC, 0x08c */ + u32 pllm_base; /* _PLLM_BASE, 0x090 */ + u32 pllm_out; /* _PLLM_OUT, 0x094 */ + u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ + u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ + u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ + u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ + u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ + u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ + u32 plla_base; /* _PLLA_BASE, 0x0b0 */ + u32 plla_out; /* _PLLA_OUT, 0x0b4 */ + u32 _rsv3; /* 0x0b8 */ + u32 plla_misc; /* _PLLA_MISC, 0x0bc */ + u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ + u32 _rsv4[2]; /* 0x0c4-0c8 */ + u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ + u32 plld_base; /* _PLLD_BASE, 0x0d0 */ + u32 _rsv5[2]; /* 0x0d4-0d8 */ + u32 plld_misc; /* _PLLD_MISC, 0x0dc */ + u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ + u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ + u32 plle_base; /* _PLLE_BASE, 0x0e8 */ + u32 plle_misc; /* _PLLE_MISC, 0x0ec */ + u32 plls_base; /* _PLLS_BASE, 0x0f0 */ + u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ + u32 _rsv6[2]; /* 0x0f8-0fc */ + u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ + u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ + u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ + u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ + u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ + u32 _rsv7; /* 0x114 */ + u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ + u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ + u32 _rsv8; /* 0x120 */ + u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ + u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ + u32 _rsv9[2]; /* 0x12c-130 */ + u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ + u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ + u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ + u32 _rsv10[2]; /* 0x140-144 */ + u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ + u32 _rsv11; /* 0x14c */ + u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ + u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ + u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ + u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ + u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ + u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ + u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ + u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ + u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ + u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ + u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ + u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ + u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ + u32 _rsv12[2]; /* 0x184-188 */ + u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ + u32 _rsv13[2]; /* 0x190-194 */ + u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ + u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ + u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ + u32 _rsv14; /* 0x1a4 */ + u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ + u32 _rsv15[2]; /* 0x1ac-1b0 */ + u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ + u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ + u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ + u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ + u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ + u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ + u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ + u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ + u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ + u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ + u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ + u32 _rsv16[4]; /* 0x1e0-1ec */ + u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ + u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ + u32 _rsv17; /* 0x1f8 */ + u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ + u32 _rsv18[32]; /* 0x200-27c */ + u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + u32 rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + u32 _rsv19[23]; /* 0x298-2f0 */ + u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + u32 _rsv20[2]; /* 0x2f8-2fc */ + u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ + u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ + u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ + u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ + u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ + u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ + u32 _rsv21[2]; /* 0x318-31c */ + u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ + u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ + u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ + u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ + u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ + u32 clk_enb_u_clk; /* _CLK_ENB_U_CLR 0x334 */ + u32 _rsv22; /* 0x338 */ + u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ + u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ + u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ + u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ + u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ + u32 _rsv23[2]; /* 0x350-354 */ + u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ + u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ + u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ + u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ + u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ + u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ + u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ + u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ + u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ + u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ + u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ + u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ + u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ + u32 _rsv24[9]; /* 0x38c-3ac */ + u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ + u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ + u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ + u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ + u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ + u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ + u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ + u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ + u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ + u32 _rsv25; /* 0x3d4 */ + u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ + u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ + u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ + u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ + u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ + u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ + u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ + u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ + u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ + u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ + u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ + u32 _rsv26[7]; /* 0x404-41c */ + u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ + u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ + u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ + u32 _rsv27; /* 0x42c */ + u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ + u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ + u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ + u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ + u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ + u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ + u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ + u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ + u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ + u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ + u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ + u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ + u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ + u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ + u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ + u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ + u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ + u32 _rsv28; /* 0x474 */ + u32 intstatus; /* _INTSTATUS, 0x478 */ + u32 intmask; /* _INTMASK, 0x47c */ + u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ + u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ + u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ + u32 plle_aux; /* _PLLE_AUX, 0x48c */ + u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ + u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ + u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ + u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ + u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ + u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ + u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ + u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ + u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ + u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ + u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ + u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ + u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ + u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ + u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ + u32 _rsv29[7]; /* 0x4cc-4e4 */ + u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ + u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ + u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ + u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ + u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ + u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ + u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ + u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ + u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ + u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ + u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ + u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ + u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ + u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ + u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ + u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ + u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ + u32 _rsv30; /* 0x538 */ + u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ + u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ + u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ + u32 _rsv31; /* 0x554 */ + u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ + u32 spare_reg0; /* _SPARE_REG0, 0x55c */ + u32 _rsv32[40]; /* 0x560-5fc */ + u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ + u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ + u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ + u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ + u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ + u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ + u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ + u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ + u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ + u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ + u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ + u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ + u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ + u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ + u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ + u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ + u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ + u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ }; #define TEGRA_DEV_L 0 diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 53eff7ede6..e1484b3d1d 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -79,7 +79,7 @@ static void clock_ll_set_source_divisor(u32 *reg, static int clock_get_osc_freq(void) { u32 reg; - reg = readl(&clk_rst->crc_osc_ctrl); + reg = readl(&clk_rst->osc_ctrl); reg >>= OSC_CTRL_OSC_FREQ_SHIFT; return reg; } @@ -87,40 +87,38 @@ static int clock_get_osc_freq(void) static void adjust_pllp_out_freqs(void) { u32 reg; - struct clk_pll *pll = &clk_rst->crc_pll[2/*CLOCK_ID_PERIPH*/]; /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ - reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */ + reg = readl(&clk_rst->pllp_outa); // OUTA contains OUT2 / OUT1 reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR; - writel(reg, &pll->pll_out[0]); + writel(reg, &clk_rst->pllp_outa); - reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */ + reg = readl(&clk_rst->pllp_outb); // OUTB, contains OUT4 / OUT3 reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR; - writel(reg, &pll->pll_out[1]); + writel(reg, &clk_rst->pllp_outb); } -static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, - u32 divp, u32 cpcon) +static int pllx_set_rate(u32 divn, u32 divm, u32 divp, u32 cpcon) { u32 reg; /* If PLLX is already enabled, just return */ - if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { + if (readl(&clk_rst->pllx_base) & PLL_ENABLE_MASK) { return 0; } /* Disable IDDQ */ - reg = readl(&clk_rst->crc_pllx_misc3); + reg = readl(&clk_rst->pllx_misc3); reg &= ~PLLX_IDDQ_MASK; - writel(reg, &clk_rst->crc_pllx_misc3); + writel(reg, &clk_rst->pllx_misc3); udelay(2); /* Set BYPASS, m, n and p to PLLX_BASE */ reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT); reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT)); - writel(reg, &pll->pll_base); + writel(reg, &clk_rst->pllx_base); /* Set cpcon to PLLX_MISC */ reg = (cpcon << PLL_CPCON_SHIFT); @@ -128,43 +126,35 @@ static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, /* Set dccon to PLLX_MISC if freq > 600MHz - still needed for T124? */ if (divn > 600) reg |= (1 << PLL_DCCON_SHIFT); - writel(reg, &pll->pll_misc); + writel(reg, &clk_rst->pllx_misc); /* Disable BYPASS */ - reg = readl(&pll->pll_base); + reg = readl(&clk_rst->pllx_base); reg &= ~PLL_BYPASS_MASK; - writel(reg, &pll->pll_base); + writel(reg, &clk_rst->pllx_base); /* Set lock_enable to PLLX_MISC */ - reg = readl(&pll->pll_misc); + reg = readl(&clk_rst->pllx_misc); reg |= PLL_LOCK_ENABLE_MASK; - writel(reg, &pll->pll_misc); + writel(reg, &clk_rst->pllx_misc); /* Enable PLLX last, as per JZ */ - reg = readl(&pll->pll_base); + reg = readl(&clk_rst->pllx_base); reg |= PLL_ENABLE_MASK; - writel(reg, &pll->pll_base); + writel(reg, &clk_rst->pllx_base); return 0; } static void init_pllx(void) { - int osc; - struct clk_pll_table *sel; - struct clk_pll_simple *pll = &clk_rst->crc_pll_simple[0/*SIMPLE_PLLX*/]; + int osc = clock_get_osc_freq(); + struct clk_pll_table *sel = &tegra_pll_x_table[osc]; - - /* get osc freq */ - osc = clock_get_osc_freq(); - - /* set pllx */ - sel = &tegra_pll_x_table[osc]; - if (sel->n == 0){ + if (sel->n == 0) return; - } - pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); + pllx_set_rate(sel->n, sel->m, sel->p, sel->cpcon); adjust_pllp_out_freqs(); } @@ -174,11 +164,11 @@ void clock_uart_config(void) /* Enable clocks to required peripherals. TBD - minimize this list */ /* The UART is super special so Just Do It right here. */ - setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); - setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK); - clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2); + setbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + clock_ll_set_source_divisor(&clk_rst->clk_src_uarta, 0, 2); udelay(2); - clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); } void clock_cpu0_config_and_reset(void *entry) @@ -187,7 +177,7 @@ void clock_cpu0_config_and_reset(void *entry) write32((uintptr_t)entry, evp_cpu_reset); // Wait for PLLX to lock. - while (!(readl(&clk_rst->crc_pll_simple[0].pll_base) & (0x1 << 27))) + while (!(readl(&clk_rst->pllx_base) & (0x1 << 27))) ; // Set up cclk_brst and divider. @@ -196,23 +186,23 @@ void clock_cpu0_config_and_reset(void *entry) (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), - &clk_rst->crc_cclk_brst_pol); + &clk_rst->cclk_brst_pol); write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, - &clk_rst->crc_super_cclk_div); + &clk_rst->super_cclk_div); // Enable the clocks for CPUs 0-3. - uint32_t cpu_cmplx_clr = read32(&clk_rst->crc_clk_cpu_cmplx_clr); + uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; - write32(cpu_cmplx_clr, &clk_rst->crc_clk_cpu_cmplx_clr); + write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); // Enable other CPU related clocks. - setbits_le32(clkenable(CLK_CPU_REG), CLK_CPU_MASK); - setbits_le32(clkenablevw(CLK_VW_CPUG_REG), CLK_VW_CPUG_MASK); + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); // Disable the reset on the non-CPU parts of the fast cluster. write32(CRC_RST_CPUG_CLR_NONCPU, - &clk_rst->crc_rst_cpug_cmplx_clr); + &clk_rst->rst_cpug_cmplx_clr); // Disable the various resets on the CPUs. write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | @@ -223,7 +213,7 @@ void clock_cpu0_config_and_reset(void *entry) CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - &clk_rst->crc_rst_cpug_cmplx_clr); + &clk_rst->rst_cpug_cmplx_clr); } /** @@ -245,17 +235,17 @@ void clock_init(void) (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clk_rst->crc_sclk_brst_pol); + writel(val, &clk_rst->sclk_brst_pol); udelay(2); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); /* Change the oscillator drive strength */ - val = readl(&clk_rst->crc_osc_ctrl); + val = readl(&clk_rst->osc_ctrl); val &= ~OSC_XOFS_MASK; val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); - writel(val, &clk_rst->crc_osc_ctrl); + writel(val, &clk_rst->osc_ctrl); /* Ambiguous quote from u-boot. TODO: what's this mean? * "should update same value in PMC_OSC_EDPD_OVER XOFS @@ -268,68 +258,52 @@ void clock_init(void) init_pllx(); val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); - writel(val, &clk_rst->crc_clk_sys_rate); + writel(val, &clk_rst->clk_sys_rate); } void clock_config(void) { - /* fixme. The stupidity of all this ... we are reading and - * writing the same register lots of times when we could just - * one lousy write with a combined mask. Sigh. - */ - setbits_le32(clkenable(CLK_CACHE2_REG), CLK_CACHE2_MASK); - setbits_le32(clkenable(CLK_GPIO_REG), CLK_GPIO_MASK); - setbits_le32(clkenable(CLK_TMR_REG), CLK_TMR_MASK); - setbits_le32(clkenable(CLK_EMC_REG), CLK_EMC_MASK); - setbits_le32(clkenable(CLK_I2C1_REG), CLK_I2C1_MASK); - setbits_le32(clkenable(CLK_I2C2_REG), CLK_I2C2_MASK); - setbits_le32(clkenable(CLK_I2C3_REG), CLK_I2C3_MASK); - setbits_le32(clkenable(CLK_I2C5_REG), CLK_I2C5_MASK); - setbits_le32(clkenable(CLK_PMC_REG), CLK_PMC_MASK); - setbits_le32(clkenable(CLK_APBDMA_REG), CLK_APBDMA_MASK); - setbits_le32(clkenable(CLK_MEM_REG), CLK_MEM_MASK); - setbits_le32(clkenable(CLK_CSITE_REG), CLK_CSITE_MASK); - setbits_le32(clkenablevw(CLK_VW_MSELECT_REG), CLK_VW_MSELECT_MASK); - setbits_le32(clkenablevw(CLK_VW_DVFS_REG), CLK_VW_DVFS_MASK); + /* Enable clocks for the required peripherals. */ + setbits_le32(&clk_rst->clk_out_enb_l, + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1); + setbits_le32(&clk_rst->clk_out_enb_h, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | + CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); + setbits_le32(&clk_rst->clk_out_enb_u, CLK_U_I2C3 | CLK_U_CSITE); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); + setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS); /* * Set MSELECT clock source as PLLP (00)_REG, and ask for a clock * divider that would set the MSELECT clock at 102MHz for a * PLLP base of 408MHz. */ - clock_ll_set_source_divisor(&clk_rst->crc_clk_src_vw[1], 0, + clock_ll_set_source_divisor(&clk_rst->clk_src_mselect, 0, CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); /* Give clock time to stabilize */ udelay(IO_STABILIZATION_DELAY); /* I2C1 gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->src_i2c1, 3, 16); + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c1, 3, 16); /* I2C2 gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->src_i2c2, 3, 16); + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c2, 3, 16); /* I2C3 (cam) gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->src_i2c3, 3, 16); + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 3, 16); /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->src_i2c5, 3, 16); + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c5, 3, 16); - /* Give clock time to stabilize */ + /* Give clock time to stabilize. */ udelay(IO_STABILIZATION_DELAY); - /* Take required peripherals out of reset */ - - clrbits_le32(clkreset(CLK_CACHE2_REG), CLK_CACHE2_MASK); - clrbits_le32(clkreset(CLK_GPIO_REG), CLK_GPIO_MASK); - clrbits_le32(clkreset(CLK_TMR_REG), CLK_TMR_MASK); - clrbits_le32(clkreset(CLK_EMC_REG), CLK_EMC_MASK); - clrbits_le32(clkreset(CLK_I2C1_REG), CLK_I2C1_MASK); - clrbits_le32(clkreset(CLK_I2C2_REG), CLK_I2C2_MASK); - clrbits_le32(clkreset(CLK_I2C3_REG), CLK_I2C3_MASK); - clrbits_le32(clkreset(CLK_I2C5_REG), CLK_I2C5_MASK); - clrbits_le32(clkreset(CLK_PMC_REG), CLK_PMC_MASK); - clrbits_le32(clkreset(CLK_APBDMA_REG), CLK_APBDMA_MASK); - clrbits_le32(clkreset(CLK_MEM_REG), CLK_MEM_MASK); - clrbits_le32(clkreset(CLK_CSITE_REG), CLK_CSITE_MASK); - clrbits_le32(clkresetvw(CLK_VW_MSELECT_REG), CLK_VW_MSELECT_MASK); - clrbits_le32(clkresetvw(CLK_VW_DVFS_REG), CLK_VW_DVFS_MASK); + /* Take required peripherals out of reset. */ + clrbits_le32(&clk_rst->rst_dev_l, + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1); + clrbits_le32(&clk_rst->rst_dev_h, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | + CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); + clrbits_le32(&clk_rst->rst_dev_u, CLK_U_I2C3 | CLK_U_CSITE); + clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT); + clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS); } diff --git a/src/soc/nvidia/tegra124/clock.h b/src/soc/nvidia/tegra124/clock.h index debaf6371b..0e26611747 100644 --- a/src/soc/nvidia/tegra124/clock.h +++ b/src/soc/nvidia/tegra124/clock.h @@ -17,136 +17,132 @@ #ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ #define __SOC_NVIDIA_TEGRA124_CLOCK_H__ -#define CLK_CONSTANTS(name, reg_index, reg_bit) \ - CLK_##name##_REG = reg_index, \ - CLK_##name##_MASK = (1 << reg_bit) - enum { - CLK_CONSTANTS(CPU, 0, 0), - CLK_CONSTANTS(COP, 0, 1), - CLK_CONSTANTS(TRIG_SYS, 0, 2), - CLK_CONSTANTS(RTC, 0, 4), - CLK_CONSTANTS(TMR, 0, 5), - CLK_CONSTANTS(UARTA, 0, 6), - CLK_CONSTANTS(UARTB, 0, 7), - CLK_CONSTANTS(GPIO, 0, 8), - CLK_CONSTANTS(SDMMC2, 0, 9), - CLK_CONSTANTS(SPDIF, 0, 10), - CLK_CONSTANTS(I2S1, 0, 11), - CLK_CONSTANTS(I2C1, 0, 12), - CLK_CONSTANTS(NDFLASH, 0, 13), - CLK_CONSTANTS(SDMMC1, 0, 14), - CLK_CONSTANTS(SDMMC4, 0, 15), - CLK_CONSTANTS(PWM, 0, 17), - CLK_CONSTANTS(I2S2, 0, 18), - CLK_CONSTANTS(EPP, 0, 19), - CLK_CONSTANTS(VI, 0, 20), - CLK_CONSTANTS(2D, 0, 21), - CLK_CONSTANTS(USBD, 0, 22), - CLK_CONSTANTS(ISP, 0, 23), - CLK_CONSTANTS(3D, 0, 24), - CLK_CONSTANTS(DISP2, 0, 26), - CLK_CONSTANTS(DISP1, 0, 27), - CLK_CONSTANTS(HOST1X, 0, 28), - CLK_CONSTANTS(VCP, 0, 29), - CLK_CONSTANTS(I2S0, 0, 30), - CLK_CONSTANTS(CACHE2, 0, 31), + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S1 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S2 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S0 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, - CLK_CONSTANTS(MEM, 1, 0), - CLK_CONSTANTS(AHBDMA, 1, 1), - CLK_CONSTANTS(APBDMA, 1, 2), - CLK_CONSTANTS(KBC, 1, 4), - CLK_CONSTANTS(STAT_MON, 1, 5), - CLK_CONSTANTS(PMC, 1, 6), - CLK_CONSTANTS(FUSE, 1, 7), - CLK_CONSTANTS(KFUSE, 1, 8), - CLK_CONSTANTS(SBC1, 1, 9), - CLK_CONSTANTS(SNOR, 1, 10), - CLK_CONSTANTS(JTAG2TBC, 1, 11), - CLK_CONSTANTS(SBC2, 1, 12), - CLK_CONSTANTS(SBC3, 1, 14), - CLK_CONSTANTS(I2C5, 1, 15), - CLK_CONSTANTS(DSI, 1, 16), - CLK_CONSTANTS(HSI, 1, 18), - CLK_CONSTANTS(HDMI, 1, 19), - CLK_CONSTANTS(CSI, 1, 20), - CLK_CONSTANTS(I2C2, 1, 22), - CLK_CONSTANTS(UARTC, 1, 23), - CLK_CONSTANTS(MIPI_CAL, 1, 24), - CLK_CONSTANTS(EMC, 1, 25), - CLK_CONSTANTS(USB2, 1, 26), - CLK_CONSTANTS(USB3, 1, 27), - CLK_CONSTANTS(MPE, 1, 28), - CLK_CONSTANTS(VDE, 1, 29), - CLK_CONSTANTS(BSEA, 1, 30), - CLK_CONSTANTS(BSEV, 1, 31), + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, - CLK_CONSTANTS(UARTD, 2, 1), - CLK_CONSTANTS(UARTE, 2, 2), - CLK_CONSTANTS(I2C3, 2, 3), - CLK_CONSTANTS(SBC4, 2, 4), - CLK_CONSTANTS(SDMMC3, 2, 5), - CLK_CONSTANTS(PCIE, 2, 6), - CLK_CONSTANTS(OWR, 2, 7), - CLK_CONSTANTS(AFI, 2, 8), - CLK_CONSTANTS(CSITE, 2, 9), - CLK_CONSTANTS(PCIEXCLK, 2, 10), - CLK_CONSTANTS(AVPUCQ, 2, 11), - CLK_CONSTANTS(TRACECLKIN, 2, 13), - CLK_CONSTANTS(SOC_THERM, 2, 14), - CLK_CONSTANTS(DTV, 2, 15), - CLK_CONSTANTS(NAND_SPEED, 2, 16), - CLK_CONSTANTS(I2C_SLOW, 2, 17), - CLK_CONSTANTS(DSIB, 2, 18), - CLK_CONSTANTS(TSEC, 2, 19), - CLK_CONSTANTS(IRAMA, 2, 20), - CLK_CONSTANTS(IRAMB, 2, 21), - CLK_CONSTANTS(IRAMC, 2, 22), + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, // Clock reset. - CLK_CONSTANTS(EMUCIF, 2, 23), + CLK_U_EMUCIF = 0x1 << 23, // Clock enable. - CLK_CONSTANTS(IRAMD, 2, 23), + CLK_U_IRAMD = 0x1 << 23, - CLK_CONSTANTS(CRAM2, 2, 24), - CLK_CONSTANTS(XUSB_HOST, 2, 25), - CLK_CONSTANTS(MSENC, 2, 27), - CLK_CONSTANTS(SUS_OUT, 2, 28), - CLK_CONSTANTS(DEV2_OUT, 2, 29), - CLK_CONSTANTS(DEV1_OUT, 2, 30), - CLK_CONSTANTS(XUSB_DEV, 2, 31), + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, - CLK_CONSTANTS(VW_CPUG, 0, 0), - CLK_CONSTANTS(VW_CPULP, 0, 1), - CLK_CONSTANTS(VW_3D2, 0, 2), - CLK_CONSTANTS(VW_MSELECT, 0, 3), - CLK_CONSTANTS(VW_I2S3, 0, 5), - CLK_CONSTANTS(VW_I2S4, 0, 6), - CLK_CONSTANTS(VW_I2C4, 0, 7), - CLK_CONSTANTS(VW_SBC5, 0, 8), - CLK_CONSTANTS(VW_SBC6, 0, 9), - CLK_CONSTANTS(VW_AUDIO, 0, 10), - CLK_CONSTANTS(VW_APBIF, 0, 11), - CLK_CONSTANTS(VW_DAM0, 0, 12), - CLK_CONSTANTS(VW_DAM1, 0, 13), - CLK_CONSTANTS(VW_DAM2, 0, 14), - CLK_CONSTANTS(VW_HDA2CODEC_2X, 0, 15), - CLK_CONSTANTS(VW_ATOMICS, 0, 16), - CLK_CONSTANTS(VW_ACTMON, 0, 23), - CLK_CONSTANTS(VW_SATA, 0, 28), - CLK_CONSTANTS(VW_HDA, 0, 29), + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S3 = 0x1 << 5, + CLK_V_I2S4 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AUDIO = 0x1 << 10, + CLK_V_APBIF = 0x1 << 11, + CLK_V_DAM0 = 0x1 << 12, + CLK_V_DAM1 = 0x1 << 13, + CLK_V_DAM2 = 0x1 << 14, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, - CLK_CONSTANTS(VW_HDA2HDMICODEC, 1, 0), - CLK_CONSTANTS(VW_SATACOLD, 1, 1), - CLK_CONSTANTS(VW_CEC, 1, 8), - CLK_CONSTANTS(VW_XUSB_PADCTL, 1, 14), - CLK_CONSTANTS(VW_ENTROPY, 1, 21), - CLK_CONSTANTS(VW_AMX0, 1, 25), - CLK_CONSTANTS(VW_ADX0, 1, 26), - CLK_CONSTANTS(VW_DVFS, 1, 27), - CLK_CONSTANTS(VW_XUSB_SS, 1, 28), - CLK_CONSTANTS(VW_MC1, 1, 30), - CLK_CONSTANTS(VW_EMC1, 1, 31), + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_AMX0 = 0x1 << 25, + CLK_W_ADX0 = 0x1 << 26, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + CLK_W_MC1 = 0x1 << 30, + CLK_W_EMC1 = 0x1 << 31 }; /* PLL stabilization delay in usec */ @@ -162,14 +158,6 @@ enum { /* soc-specific */ #define NVBL_PLLP_KHZ (408000) -/* make this a macro, rather than a function; let the C compiler find - * the error for you if you use an out of range index.. Requires you - * to declare a clk_rst pointer. */ -#define clkreset(x) &clk_rst->crc_rst_dev[(x)] -#define clkenable(x) &clk_rst->crc_clk_out_enb[(x)] -#define clkresetvw(x) &clk_rst->crc_rst_dev_vw[(x)] -#define clkenablevw(x) &clk_rst->crc_clk_out_enb_vw[(x)] - void clock_uart_config(void); void clock_cpu0_config_and_reset(void * entry); void clock_config(void);