From 9203cc827f9881dc7a19b640364510581a299234 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Thu, 11 Dec 2025 17:13:54 +0800 Subject: [PATCH] soc/mediatek/mt8196: Add MTE tag memory to bootmem This patch enables MTE (Memory Tagging Extension) for the MediaTek MT8196 SoC. During `soc_init`, it calculates the required size and start address for the MTE tag storage based on the physical DRAM size. It then calls `booker_mte_init` to initialize the MTE hardware with the calculated start address. Later, during memory initialization, `bootmem_platform_add_ranges` uses `bootmem_add_range_from` to reserve the calculated memory region for MTE tag storage, preventing it from being used for other purposes. BUG=b:438666196 TEST=Check cbmem log. [DEBUG] booker_mte_init: MTE tag addr 0x460f70000 ... [DEBUG] 17. 0000000460f70000-000000047ffeffff: TAG STORAGE [DEBUG] 18. 000000047fff0000-000000047fffffff: RESERVED Change-Id: I7caa4fde4f314261383a68e942b0e3fb06c6184b Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/90144 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) Reviewed-by: Chen-Tsung Hsieh Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/dramc_info.c | 2 +- .../mediatek/common/include/soc/dramc_info.h | 4 ++++ src/soc/mediatek/mt8196/soc.c | 19 ++++++++++++++++++- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/common/dramc_info.c b/src/soc/mediatek/common/dramc_info.c index d64796370f..fc4ab9cc72 100644 --- a/src/soc/mediatek/common/dramc_info.c +++ b/src/soc/mediatek/common/dramc_info.c @@ -12,7 +12,7 @@ void reserve_buffer_for_dramc(void) { const struct mem_chip_info *mc = cbmem_find(CBMEM_ID_MEM_CHIP_INFO); int i; - const uint32_t reserved_size = 64 * KiB; + const uint32_t reserved_size = HW_TX_TRACING_BUF_SIZE; uint64_t cbmem_top_addr = cbmem_top(); uint64_t reserved_addr; uint64_t rank_size_sum = 0; diff --git a/src/soc/mediatek/common/include/soc/dramc_info.h b/src/soc/mediatek/common/include/soc/dramc_info.h index a0be6403e5..77ab0dc140 100644 --- a/src/soc/mediatek/common/include/soc/dramc_info.h +++ b/src/soc/mediatek/common/include/soc/dramc_info.h @@ -3,6 +3,10 @@ #ifndef __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ #define __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ +#include + +#define HW_TX_TRACING_BUF_SIZE (64 * KiB) + void reserve_buffer_for_dramc(void); #endif /* __SOC_MEDIATEK_COMMON_DRAMC_INFO_H__ */ diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 1fbe09025f..bacbe0c2c5 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -19,6 +19,9 @@ #include #include +static uint64_t mte_start; +static size_t mte_size; + void bootmem_platform_add_ranges(void) { if (CONFIG(ARM64_BL31_OPTEE_WITH_SMC)) @@ -30,6 +33,8 @@ void bootmem_platform_add_ranges(void) bootmem_add_range((uint64_t)_resv_mem_gpu, REGION_SIZE(resv_mem_gpu), BM_MEM_RESERVED); bootmem_add_range((uint64_t)_resv_mem_gpueb, REGION_SIZE(resv_mem_gpueb), BM_MEM_RESERVED); + + bootmem_add_range_from(mte_start, mte_size, BM_MEM_TAG, BM_MEM_RAM); } static void soc_read_resources(struct device *dev) @@ -37,6 +42,18 @@ static void soc_read_resources(struct device *dev) ram_range(dev, 0, (uintptr_t)_dram, sdram_size()); } +#define MTE_SIZE_ALIGNMENT (64 * KiB) + +static void mte_setup(void) +{ + size_t dram_size = sdram_size(); + + mte_size = ALIGN_UP(dram_size / 33, MTE_SIZE_ALIGNMENT); + mte_start = ALIGN_DOWN((uint64_t)_dram + dram_size - mte_size - HW_TX_TRACING_BUF_SIZE, + MTE_SIZE_ALIGNMENT); + booker_mte_init(mte_start); +} + static void soc_init(struct device *dev) { uint32_t storage_type = mainboard_get_storage_type(); @@ -57,7 +74,7 @@ static void soc_init(struct device *dev) * Registers are only accessible by Secure accesses. Writes to them must occur prior to * the first non-configuration access targeting the device. */ - booker_mte_init(MTE_TAG_ADDR); + mte_setup(); } static struct device_operations soc_ops = {