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mb/dell: Add Latitude E6220 (Sandy Bridge)

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Mainboard is codenamed Vida. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. The VBT was obtained using
intelvbttool while running version A14 (latest available version) of the
vendor firmware.

Tested and found to boot as part of a libreboot build based on upstream
coreboot commit b7341da191 with additional patches, though these do not
appear to affect SNB/IVB. The base E6430 patch was tested against
coreboot main.

The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].

[1] https://gitlab.com/nic3-14159/dell-flash-unlock

Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nicholas Chin 2024-03-08 09:27:36 -07:00 • committed by Felix Singer
commit 908c1b0b8e
7 changed files with 287 additions and 0 deletions
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9
src/mainboard/dell/snb_ivb_latitude/Kconfig
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@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
select BOARD_ROMSIZE_KB_6144
select SOUTHBRIDGE_INTEL_BD82X6X
config BOARD_DELL_LATITUDE_E6220
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_10240
select MAINBOARD_USES_IFD_GBE_REGION
select SOUTHBRIDGE_INTEL_BD82X6X
config BOARD_DELL_LATITUDE_E6320
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_10240
@ -73,6 +79,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220
default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
@ -89,6 +96,7 @@ config USBDEBUG_HCD_INDEX
config VARIANT_DIR
default "e5420" if BOARD_DELL_LATITUDE_E5420
default "e5520" if BOARD_DELL_LATITUDE_E5520
default "e6220" if BOARD_DELL_LATITUDE_E6220
default "e6320" if BOARD_DELL_LATITUDE_E6320
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
@ -102,6 +110,7 @@ config VGA_BIOS_ID
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
|| BOARD_DELL_LATITUDE_E5520 \
|| BOARD_DELL_LATITUDE_E6220 \
|| BOARD_DELL_LATITUDE_E6320
default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
|| BOARD_DELL_LATITUDE_E6530

3
src/mainboard/dell/snb_ivb_latitude/Kconfig.name
View file

@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
config BOARD_DELL_LATITUDE_E5520
bool "Latitude E5520"
config BOARD_DELL_LATITUDE_E6220
bool "Latitude E6220"
config BOARD_DELL_LATITUDE_E6320
bool "Latitude E6320"

BIN
src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt Normal file
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Binary file not shown.

14
src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c Normal file
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@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <ec/dell/mec5035/mec5035.h>
#include <southbridge/intel/bd82x6x/pch.h>
void bootblock_mainboard_early_init(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
mec5035_early_init();
}

192
src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c Normal file
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@ -0,0 +1,192 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_NATIVE,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_NATIVE,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_NATIVE,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_GPIO,
.gpio31 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_INPUT,
.gpio29 = GPIO_DIR_INPUT,
.gpio30 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio30 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio1 = GPIO_INVERT,
.gpio8 = GPIO_INVERT,
.gpio14 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_NATIVE,
.gpio44 = GPIO_MODE_NATIVE,
.gpio45 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_NATIVE,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_NATIVE,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_NATIVE,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_NATIVE,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_GPIO,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio33 = GPIO_DIR_INPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_OUTPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_OUTPUT,
.gpio51 = GPIO_DIR_INPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio34 = GPIO_LEVEL_HIGH,
.gpio45 = GPIO_LEVEL_LOW,
.gpio49 = GPIO_LEVEL_LOW,
.gpio60 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_NATIVE,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

32
src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c Normal file
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@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x111d76e7, /* Codec Vendor / Device ID: IDT */
0x102804a9, /* Subsystem ID */
11, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x102804a9),
AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
0x80862805, /* Codec Vendor / Device ID: Intel */
0x80860101, /* Subsystem ID */
4, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(3, 0x80860101),
AZALIA_PIN_CFG(3, 0x05, 0x18560010),
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

37
src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb Normal file
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@ -0,0 +1,37 @@
## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1028 0x04a9 inherit
device ref igd on
register "gpu_cpu_backlight" = "0x0000046a"
register "gpu_pch_backlight" = "0x13121312"
end
chip southbridge/intel/bd82x6x
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "usb_port_config" = "{
{ 1, 1, 0 },
{ 1, 0, 0 },
{ 1, 1, 1 },
{ 1, 0, 1 },
{ 1, 1, 2 },
{ 1, 1, 2 },
{ 1, 1, 3 },
{ 1, 1, 3 },
{ 1, 0, 5 },
{ 1, 0, 5 },
{ 1, 1, 7 },
{ 1, 1, 6 },
{ 1, 0, 6 },
{ 1, 0, 7 },
}"
device ref pcie_rp4 off end
device ref sata1 on
register "sata_port_map" = "0x3b"
end
end
end
end