From 8f7ff90f8e7146c6991c410265a3b2e05ba5a17b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Jul 2016 15:38:37 +0300 Subject: [PATCH] UPSTREAM: intel/haswell post-car: Minor fix on MTRR setting Change-Id: I65f0ad430bdcc2065c1e873743da04201a68d9c9 Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/15796 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/362766 Reviewed-by: Furquan Shaikh --- src/cpu/intel/haswell/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b15ed546e..a05d570ac8 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -69,7 +69,7 @@ static inline u32 *stack_push(u32 *stack, u32 value) * cache-as-ram is torn down as well as the MTRR settings to use. */ static void *setup_romstage_stack_after_car(void) { - unsigned long top_of_stack; + uintptr_t top_of_stack; int num_mtrrs; u32 *slot; u32 mtrr_mask_upper; @@ -82,7 +82,7 @@ static void *setup_romstage_stack_after_car(void) /* The upper bits of the MTRR mask need to set according to the number * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1; /* The order for each MTRR is value then base with upper 32-bits of * each value coming before the lower 32-bits. The reasoning for