From 8f51827d56f7b7542e10cd5cc6b2cf389a4e8c7b Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 18 Sep 2015 12:46:01 -0700 Subject: [PATCH] rk3288: Add 600MHz as an option for RK3288 APLL BUG=chrome-os-partner:41201 BRANCH=firmware-veyron TEST=tested with subsequent patch on mickey Signed-off-by: David Hendricks Change-Id: I3ce0f7b2772c8c652b7f461749d01cc7b669b6cf Reviewed-on: https://chromium-review.googlesource.com/300786 Reviewed-by: Julius Werner Commit-Queue: David Hendricks Tested-by: David Hendricks --- src/soc/rockchip/rk3288/clock.c | 2 ++ src/soc/rockchip/rk3288/include/soc/clock.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 642dc5b21b..e0673317df 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -78,9 +78,11 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); /* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */ static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1); static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1); +static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2); static const struct pll_div *apll_cfgs[] = { [APLL_1800_MHZ] = &apll_1800_cfg, [APLL_1392_MHZ] = &apll_1392_cfg, + [APLL_600_MHZ] = &apll_600_cfg, }; /*******************PLL CON0 BITS***************************/ diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index dc9cf5ef36..d1c51cfc25 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -31,6 +31,7 @@ enum apll_frequencies { APLL_1800_MHZ, APLL_1392_MHZ, + APLL_600_MHZ, }; /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */