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UPSTREAM: soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree

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BUG=None
BRANCH=None
TEST=None

Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15055
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358597
Reviewed-by: Martin Roth <martinroth@chromium.org>
This commit is contained in:
Saurabh Satija 2016-05-03 15:15:31 -07:00 • committed by chrome-bot
commit 8eed6534f0
2 changed files with 5 additions and 0 deletions
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2
src/soc/intel/apollolake/chip.c
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@ -332,6 +332,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
}

3
src/soc/intel/apollolake/chip.h
View file

@ -101,6 +101,9 @@ struct soc_intel_apollolake_config {
uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
/* Configure LPSS S0ix Enable */
uint8_t lpss_s0ix_enable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */