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UPSTREAM: sb/lynxpoint: add missing USB port defs

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Add device/address stubs for XHCI USB ports 7, 10-13.
Stub data will be supplemented by board-specific info
added in subsequent commits.

BUG=none
BRANCH=none
TEST=none

Change-Id: I1836298d69bb87fab1cc024e94aab1eb3410075b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a672d155a2
Original-Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19965
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/521037
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Matt DeVillier 2017-04-17 18:26:58 -05:00 • committed by chrome-bot
commit 8e38aa70ab
1 changed files with 5 additions and 2 deletions
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7
src/southbridge/intel/lynxpoint/acpi/usb.asl
View file

@ -49,7 +49,6 @@ Device (EHCI)
{
Name (_ADR, 0x00000000)
// How many are there?
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
@ -409,12 +408,16 @@ Device (XHCI)
Return (PCKG)
}
// How many are there?
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5
Device (PRT7) { Name (_ADR, 7) } // USB Port 6
Device (SSP1) { Name (_ADR, 10) } // USB Port 10
Device (SSP2) { Name (_ADR, 11) } // USB Port 11
Device (SSP3) { Name (_ADR, 12) } // USB Port 12
Device (SSP4) { Name (_ADR, 13) } // USB Port 13
}
}