diff --git a/src/arch/i386/lib/hardwaremain.c b/src/arch/i386/lib/hardwaremain.c
index cf07555127..0396444107 100644
--- a/src/arch/i386/lib/hardwaremain.c
+++ b/src/arch/i386/lib/hardwaremain.c
@@ -67,6 +67,18 @@ void intel_main()
 	int intel_l2_configure();
 #endif /* CONFIGURE_L2_CACHE */
 
+#ifdef CPU_FIXUP
+	// some cpus need a fixup done. This is the hook for doing that
+	// For now we call it after pci config and sizing. 
+	// we may move it earlier for speed. 
+	// Comment: the NEW_SUPERIO architecture is actually pretty good.
+	// I think we need to move to the same sort of architecture for
+	// everything: A config file generated sequence of calls 
+	// for initializing all the chips. We stick with this 
+	// for now -- rgm. 
+	void cpufixup(unsigned long totalram);
+#endif
+
 #ifdef UPDATE_MICROCODE
 	void intel_display_cpuid_microcode(void);
 #endif /* UPDATE_MICROCODE */
@@ -126,6 +138,10 @@ void intel_main()
 	if (!totalram)
 		totalram = 64 * 1024;
 
+#ifdef CPU_FIXUP
+	// cpu-dependent fixup. 
+	cpufixup(totalram);
+#endif
 	// Turn on cache before configuring the bus. 
 	printk(KERN_INFO "Enabling cache...");
 	intel_cache_on(0, totalram);
diff --git a/src/cpu/k7/Config b/src/cpu/k7/Config
new file mode 100644
index 0000000000..287bc09e4a
--- /dev/null
+++ b/src/cpu/k7/Config
@@ -0,0 +1,3 @@
+option k7
+option CPU_FIXUP
+object cpufixup.o
diff --git a/src/cpu/k7/cpufixup.c b/src/cpu/k7/cpufixup.c
new file mode 100644
index 0000000000..5041f4a2d0
--- /dev/null
+++ b/src/cpu/k7/cpufixup.c
@@ -0,0 +1,42 @@
+// Needed so the AMD K7 runs correctly. 
+#include <printk.h>
+#include <cpu/p6/msr.h>
+
+#define TOP_MEM 0xc001001a
+#define TOP_MEM2 0xc001001d
+#define IORR_FIRST 0xC0010016
+#define IORR_LAST 0xC0010019
+#define SYSCFG    0xc0010010
+
+#define MTRRVARDRAMEN (1 << 20)
+void
+cpufixup(unsigned long ram_megabytes)
+{
+    unsigned long lo = 0, hi = 0, i;
+	// 8 MB alignment please
+    ram_megabytes += 0x7fffff;
+    ram_megabytes &= (~0x7fffff);
+    // set top_mem registers to ram size 
+    printk(KERN_INFO "Setting top_mem to 0x%x\n", ram_megabytes);
+    rdmsr(TOP_MEM, lo, hi);
+    printk(KERN_INFO "TOPMEM was 0x%x:0x$x\n", hi, lo);
+    hi = 0;
+    lo = ram_megabytes;
+    wrmsr(TOP_MEM, lo, hi);
+    // I am setting this even though I won't enable it
+    wrmsr(TOP_MEM2, lo, hi);
+
+    /* zero the IORR's before we enable to prevent
+     * undefined side effects
+     */
+    lo = hi = 0;
+    for(i = IORR_FIRST; i < IORR_LAST; i++)
+        wrmsr(i, lo, hi);
+
+    rdmsr(SYSCFG, lo, hi);
+    printk(KERN_INFO "SYSCFG was 0x%x:0x%x\n", hi, lo);
+    lo |= MTRRVARDRAMEN;
+    wrmsr(SYSCFG, lo, hi);
+    rdmsr(SYSCFG, lo, hi);
+    printk(KERN_INFO "SYSCFG IS NOW 0x%x:0x%x\n", hi, lo);
+}
diff --git a/src/mainboard/pcchips/m810lmr/Config b/src/mainboard/pcchips/m810lmr/Config
index 283863131b..46b726a280 100644
--- a/src/mainboard/pcchips/m810lmr/Config
+++ b/src/mainboard/pcchips/m810lmr/Config
@@ -11,3 +11,4 @@ object irq_tables.o
 keyboard pc80
 cpu p5
 cpu p6
+cpu k7
diff --git a/src/northbridge/acer/m1631/northbridge.c b/src/northbridge/acer/m1631/northbridge.c
index f6b3e596b9..00efbdd5e6 100644
--- a/src/northbridge/acer/m1631/northbridge.c
+++ b/src/northbridge/acer/m1631/northbridge.c
@@ -52,7 +52,10 @@ unsigned long sizeram()
 	if ((ram & 0x1800000) == 0x1800000)
 		size <<= 1;
 	printk("size in 0x6c is 0x%x\n", size);
+#if 1
+	printk("NOT SIZING OTHER TWO SLOTS. ONLY ONE SLOT RIGHT NOW\n");
 	return size/1024;
+#endif
 	cp = (unsigned char *) size;
 	// now do the other two banks. 
 #define INIT_MCR 0xf663b83c