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drivers/spi: Add 4-byte address mode flag to lb_spi_flash

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Adds a new flags field to the lb_spi_flash coreboot table to indicate
if the SPI flash is operating in 4-byte address mode.

This allows payloads to query the current address mode directly from the
coreboot table, preventing redundant checks or re-enforcement of the
mode. The flag is set based on the
CONFIG_SPI_FLASH_FORCE_4_BYTE_ADDR_MODE configuration.

Important: `erase_cmd` was reduced from uint32_t to uint8_t.
Only the least significant byte was ever relevant, so this change
ensures accurate type representation, maintains backward compatibility
with existing coreboot table structures, and frees up space.

BUG=b:417900125
TEST=Able to build google/bluey.

Change-Id: I406536432b2a0c7f4108e5b33d5a20c272d917b0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Subrata Banik 2025-06-24 10:21:45 +00:00
commit 8dec5fcaf8
2 changed files with 13 additions and 1 deletions
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10
src/commonlib/include/commonlib/coreboot_tables.h
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@ -359,7 +359,15 @@ struct lb_spi_flash {
uint32_t size;
uint32_t flash_size;
uint32_t sector_size;
uint32_t erase_cmd;
/*
* Note: `erase_cmd` was previously a uint32_t. It's now uint8_t because only
* the lowest byte was used, ensuring backward compatibility with older coreboot
* tables and allowing reuse of the remaining bytes.
*/
uint8_t erase_cmd;
#define LB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE (1 << 0)
uint8_t flags;
uint16_t reserved;
/*
* Number of mmap windows used by the platform to decode addresses between SPI flash
* space and host address space. This determines the number of entries in mmap_table.