diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES
index 0e67dd173c..8240375e11 100644
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@@ -5,7 +5,7 @@ coreboot POST Codes
 This is an (incomplete) list of POST codes emitted by coreboot v4.
 
 0x10 Entry into protected mode
-0x01 Entry into 'crt0.s' reset code jumps to here
+0x01 Entry into 'entry16.S' reset code jumps to here
 0x11 Start copying coreboot to RAM with decompression if compressed
 0x12 Copy/decompression finished jumping to RAM
 0x80 Entry into coreboot in RAM
diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md
index 199a7da78c..a52d206636 100644
--- a/Documentation/acronyms.md
+++ b/Documentation/acronyms.md
@@ -204,7 +204,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
   (End-of-Line) marker.
 * crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
-* crt0s - crt0 Source code
 * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
 * CSE - Intel: Converged Security Engine
 * CSI - MIPI: [**Camera Serial
diff --git a/Makefile.mk b/Makefile.mk
index e83a304ca6..92098ba1b7 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -822,13 +822,6 @@ clean-abuild:
 
 #######################################################################
 # Development utilities
-printcrt0s:
-	@echo crt0s=$(crt0s)
-	@echo ldscripts=$(ldscripts)
-
-update:
-	dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
-
 check-style:
 	grep "^# DESCR:" util/lint/check-style | sed "s,.*DESCR: *,,"
 	echo "========"
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index b58907e230..8e6babceb3 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -185,7 +185,7 @@ config BOOTBLOCK_DEBUG_SPINLOOP
 	bool
 	default n
 	help
-	  Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
+	  Add a spin (JMP .) in entry32.S during early bootblock to wait
 	  for a JTAG debugger to break into the execution sequence.
 
 config HAVE_CMOS_DEFAULT
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index d581bc487f..b0f9565e35 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -34,7 +34,7 @@
 #define POSTCODE_CODE_CLEAR				0x00
 
 /**
- * \brief  Entry into 'crt0.s'. reset code jumps to here
+ * \brief  Entry into 'entry16.S'. reset code jumps to here
  *
  * First instruction that gets executed after the reset vector jumps.
  * This indicates that the reset vector points to the correct code segment.
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 8d41826bfd..9411ad0a6f 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -3,7 +3,7 @@
 /******************************************************************************
  * $Workfile:: cache_as_ram.S
  *
- * Description: CAR setup called from bootblock_crt0.S.
+ * Description: CAR setup called from entry32.S.
  *
  ******************************************************************************
  */
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index ed735dbce3..1e55039a3c 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -90,7 +90,7 @@ CAR_init_done:
 	or	%rsi, %rdi
 	andl	$0xfffffff0, %esp
 #else
-	/* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
+	/* Restore the timestamp from entry32.S (ebp:mm1) */
 	push	%ebp
 	movd	%mm1, %eax
 	push	%eax