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Following patch converts the run-time SSDT patching via update_ssdt funtion to

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new AML code generator. Compile-tested on all changed targets. I think it should
work because it works for Asus M2V-MX SE.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2009-02-03 22:37:22 +00:00
commit 8db0cfefd1
8 changed files with 48 additions and 298 deletions
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7
src/northbridge/amd/amdk8/Config.lb
View file

@ -19,13 +19,6 @@ end
if HAVE_ACPI_TABLES
object amdk8_acpi.o
makerule ssdt.c
depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
action "mv ssdt.hex ssdt.c"
end
object ./ssdt.o
end

83
src/northbridge/amd/amdk8/amdk8_acpi.c
View file

@ -308,86 +308,3 @@ int k8acpi_write_vars(void)
acpigen_patch_len(lens - 1);
return lens;
}
// moved from mb acpi_tables.c
static void intx_to_stream(u32 val, u32 len, u8 *dest)
{
int i;
for(i=0;i<len;i++) {
*(dest+i) = (val >> (8*i)) & 0xff;
}
}
static void int_to_stream(u32 val, u8 *dest)
{
return intx_to_stream(val, 4, dest);
}
// used by acpi_tables.h
void update_ssdt(void *ssdt)
{
u8 *BUSN;
u8 *MMIO;
u8 *PCIO;
u8 *SBLK;
u8 *TOM1;
u8 *SBDN;
u8 *HCLK;
u8 *HCDN;
u8 *CBST;
int i;
device_t dev;
u32 dword;
msr_t msr;
BUSN = ssdt+0x3a; //+5 will be next BUSN
MMIO = ssdt+0x57; //+5 will be next MMIO
PCIO = ssdt+0xaf; //+5 will be next PCIO
SBLK = ssdt+0xdc; // one byte
TOM1 = ssdt+0xe3; //
SBDN = ssdt+0xed; //
HCLK = ssdt+0xfa; //+5 will be next HCLK
HCDN = ssdt+0x12a; //+5 will be next HCDN
CBST = ssdt+0x157; //
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i=0;i<4;i++) {
dword = pci_read_config32(dev, 0xe0+i*4);
int_to_stream(dword, BUSN+i*5);
}
for(i=0;i<0x10;i++) {
dword = pci_read_config32(dev, 0x80+i*4);
int_to_stream(dword, MMIO+i*5);
}
for(i=0;i<0x08;i++) {
dword = pci_read_config32(dev, 0xc0+i*4);
int_to_stream(dword, PCIO+i*5);
}
*SBLK = (u8)(sysconf.sblk);
msr = rdmsr(TOP_MEM);
int_to_stream(msr.lo, TOM1);
for(i=0;i<sysconf.hc_possible_num;i++) {
int_to_stream(sysconf.pci1234[i], HCLK + i*5);
int_to_stream(sysconf.hcdn[i], HCDN + i*5);
}
for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
int_to_stream(0x00000000, HCLK + i*5);
int_to_stream(0x20202020, HCDN + i*5);
}
int_to_stream(sysconf.sbdn, SBDN);
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
*CBST = (u8) (0x0f);
}
else {
*CBST = (u8) (0x00);
}
}
//end

78
src/northbridge/amd/amdk8/ssdt.dsl
View file

@ -1,78 +0,0 @@
/*
* Copyright 2005 AMD
*/
DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
{
/*
* These objects were referenced but not defined in this table
*/
External (\_SB_.PCI0, DeviceObj)
Scope (\_SB.PCI0)
{
Name (BUSN, Package (0x04)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444
})
Name (MMIO, Package (0x10)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee,
0x11111111,
0x22222222
})
Name (PCIO, Package (0x08)
{
0x77777777,
0x88888888,
0x99999999,
0xaaaaaaaa,
0xbbbbbbbb,
0xcccccccc,
0xdddddddd,
0xeeeeeeee
})
Name (SBLK, 0x11)
Name (TOM1, 0xaaaaaaaa)
Name (SBDN, 0xbbbbbbbb)
Name (HCLK, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (HCDN, Package (0x08)
{
0x11111111,
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888
})
Name (CBST, 0x88)
}
}