diff --git a/romimages/RON_VT5259A/Makefile b/romimages/RON_VT5259A/Makefile
index c7e75e09eb..f073d7ef37 100644
--- a/romimages/RON_VT5259A/Makefile
+++ b/romimages/RON_VT5259A/Makefile
@@ -121,7 +121,7 @@ mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
 microcode.o: $(TOP)/src/cpu/p6/microcode.c
 	$(CC) $(CFLAGS) -c $<
 
-serial_subr.o: $(TOP)/chip/intel/serial_subr.c
+serial_subr.o: $(TOP)/src/lib/serial_subr.c
 	cc $(CFLAGS) -c $<
 
 printk.o: $(TOP)/src/lib/printk.c
diff --git a/romimages/RON_WINFAST6300/Makefile b/romimages/RON_WINFAST6300/Makefile
index 9e5f27746d..72f6e1f6e9 100644
--- a/romimages/RON_WINFAST6300/Makefile
+++ b/romimages/RON_WINFAST6300/Makefile
@@ -123,7 +123,7 @@ mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
 microcode.o: $(TOP)/src/cpu/p6/microcode.c
 	$(CC) $(CFLAGS) -c $<
 
-serial_subr.o: $(TOP)/chip/intel/serial_subr.c
+serial_subr.o: $(TOP)/src/lib/serial_subr.c
 	cc $(CFLAGS) -c $<
 
 printk.o: $(TOP)/src/lib/printk.c
diff --git a/romimages/WINFAST6300_FLASHROOT/Makefile b/romimages/WINFAST6300_FLASHROOT/Makefile
index 671f5f0c00..2ea6cf51d8 100644
--- a/romimages/WINFAST6300_FLASHROOT/Makefile
+++ b/romimages/WINFAST6300_FLASHROOT/Makefile
@@ -124,7 +124,7 @@ mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
 microcode.o: $(TOP)/src/cpu/p6/microcode.c
 	$(CC) $(CFLAGS) -c $<
 
-serial_subr.o: $(TOP)/chip/intel/serial_subr.c
+serial_subr.o: $(TOP)/src/lib/serial_subr.c
 	cc $(CFLAGS) -c $<
 
 printk.o: $(TOP)/src/lib/printk.c
diff --git a/romimages/WINFAST6300_SERCONS/Makefile b/romimages/WINFAST6300_SERCONS/Makefile
new file mode 100644
index 0000000000..497a131a86
--- /dev/null
+++ b/romimages/WINFAST6300_SERCONS/Makefile
@@ -0,0 +1,168 @@
+CPUFLAGS=-DSIS630 -Di386 -Di486 -Di686 -Di586  -D__KERNEL__
+CPUFLAGS += -DINTEL_BRIDGE_CONFIG -DSIS630_NVRAM
+CPUFLAGS += -DINTEL_PPRO_MTRR  -DSIS630_KEYBOARD
+# CPUFLAGS += -DMUST_ENABLE_FLOPPY
+CPUFLAGS += -DSIS_FIXUP_FOR_FB
+CPUFLAGS += -DHAVE_FRAMEBUFFER
+CPUFLAGS += -DNEWPCI
+CPUFLAGS += -DSERIAL_CONSOLE
+CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
+CPUFLAGS += -DINBUF_COPY
+CPUFLAGS += -DUSE_DOC_MIL
+CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
+CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
+
+LINUX=$(TOP)/../linux-2.4.0-test6.sis
+
+TOP=../..
+INCLUDES=-nostdinc -I $(TOP)/src/include 
+CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall
+
+OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o 
+OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
+OBJECTS += southbridge.o northbridge.o superio.o
+#OBJECTS += pci.o
+OBJECTS += printk.o vsprintf.o
+OBJECTS += newpci.o linuxpci.o
+OBJECTS += cpuid.o 
+OBJECTS += irq_tables.o
+OBJECTS += serial_subr.o
+OBJECTS += mpspec.o
+OBJECTS += microcode.o
+OBJECTS += keyboard.o
+
+LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
+CC=cc $(CFLAGS)
+CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
+
+all: romimage
+floppy: all 
+	mcopy -o romimage a:
+# here's the problem: we shouldn't assume we come up with more than 
+# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
+# enable all flash and then gunzip the linuxbios. As a result, 
+# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
+# at then end. We always copy it to /tmp so that a waiting root shell 
+# can put it on the floppy (see ROOTDOIT)
+romimage: linuxbios.rom vmlinux.bin.gz.block docipl
+	cat vmlinux.bin.gz.block linuxbios.rom > romimage
+	cp romimage /tmp
+
+docipl: ipl.o
+	objcopy -O binary -R .note -R .comment -S ipl.o docipl
+linuxbios.rom: linuxbios.strip mkrom 
+	./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
+
+linuxbios.strip: linuxbios
+	objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
+
+linuxbios: $(OBJECTS) vmlinux.bin.gz
+	@rm -f biosobject
+	$(LINK) 
+	nm -n linuxbios > linuxbios.map
+
+# crt0 actually includes .inc files. 
+# For self-documenting purposes, we put the FULL PATH of the 
+# .inc files (relative to $TOP/src) in crt0.S. 
+# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
+# To make this work, add the extra -I $(TOP)/src here. 
+crt0.s: $(TOP)/src/mainboard/leadtek/winfast6300/crt0.S 
+	$(CCASM) -I $(TOP)/src -E $< > crt0.s
+
+crt0.o : crt0.s
+	$(CCASM) -c crt0.s
+
+mkrom: $(TOP)/mkrom/mkrom.c
+	cc -o mkrom $<
+
+linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
+	cc $(CFLAGS) -c $<
+
+mainboard.o: $(TOP)/src/mainboard/leadtek/winfast6300/mainboard.c
+	cc $(CFLAGS) -c $<
+
+fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
+	cc $(CFLAGS) -c $<
+
+params.o: $(TOP)/src/lib/params.c
+	cc $(CFLAGS) $(LINUXINCLUDE) -c $<
+
+hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
+	cc $(CFLAGS) -c $<
+
+southbridge.o: $(TOP)/src/northsouthbridge/sis/630/southbridge.c
+	cc $(CFLAGS) -c $<
+
+northbridge.o: $(TOP)/src/northsouthbridge/sis/630/northbridge.c
+	cc $(CFLAGS) -c $<
+
+superio.o: $(TOP)/src/superio/sis/950/superio.c
+	cc $(CFLAGS) -c $<
+
+pci.o:  $(TOP)/src/lib/pci.c
+	cc $(CFLAGS) -c $<
+
+
+irq_tables.o: $(TOP)/src/mainboard/leadtek/winfast6300/irq_tables.c
+	cc $(CFLAGS) -o $@ -c $<
+
+mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
+	cc $(CFLAGS) -c $<
+
+subr.o: $(TOP)/src/lib/subr.c
+	cc $(CFLAGS) -c $<
+
+keyboard.o: $(TOP)/src/pc80/keyboard.c
+	cc $(CFLAGS) -c $<
+
+cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
+	cc $(CFLAGS) -c $<
+
+mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
+	$(CC) $(CFLAGS) -c $<
+
+microcode.o: $(TOP)/src/cpu/p6/microcode.c
+	$(CC) $(CFLAGS) -c $<
+
+serial_subr.o: $(TOP)/src/lib/serial_subr.c
+	cc $(CFLAGS) -c $<
+
+printk.o: $(TOP)/src/lib/printk.c
+	cc $(CFLAGS) -c $<
+
+vsprintf.o: $(TOP)/src/lib/vsprintf.c
+	cc $(CFLAGS) -c $<
+
+newpci.o: $(TOP)/src/lib/newpci.c
+	cc $(CFLAGS) -c $<
+
+linuxpci.o: $(TOP)/src/lib/linuxpci.c
+	cc $(CFLAGS) -c $<
+
+ipl.o: $(TOP)/src/northsouthbridge/sis/630/ipl.S
+	gcc -c -I$(TOP)/northsouthbridge/sis/630 $<
+
+vmlinux.bin.gz.block: vmlinux.bin.gz
+	dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
+vmlinux.bin.gz: vmlinux.bin
+	gzip -f -3 vmlinux.bin 
+
+vmlinux.bin: $(LINUX)/vmlinux
+	objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
+
+alltags: 
+	gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
+	etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
+
+
+clean:: 
+	rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
+	rm -f a.out *.s *.l
+	rm -f TAGS tags
+	rm -f docipl
+
+
+
+
+
+
diff --git a/romimages/WINFAST6300_SERCONS/ldscript.ld b/romimages/WINFAST6300_SERCONS/ldscript.ld
new file mode 100644
index 0000000000..9c5739ca14
--- /dev/null
+++ b/romimages/WINFAST6300_SERCONS/ldscript.ld
@@ -0,0 +1,114 @@
+/*
+ * Bootstrap code for the STPC Consumer
+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
+ *
+ * $Id$
+ *
+ */
+/* oh, barf. This won't work if all you use is .o's.  -- RGM */
+
+/*
+ *	Written by Johan Rydberg, based on work by Daniel Kahlin.
+ */
+/*
+ *	We use ELF as output format. So that we can
+ *	debug the code in some form. 
+ */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+
+/*
+ *	Memory map:
+ *
+ *	0x00000	(4*4096 bytes)	: stack
+ *	0x04000	(4096 bytes)	: private data 
+ *	0x05000			: data space
+ *	0x90000			: kernel stack
+ *	0xf0000	(64 Kbyte)	: EPROM
+ */
+MEMORY
+{
+	ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M	/* 128 MB memory is max for STPC */
+	rom (rx)  : ORIGIN = 0x000f0000, LENGTH = 128K	/* 128 K EPROM */
+}
+
+_PDATABASE	= 0x04000;
+_RAMBASE	= 0x05000;
+_KERNSTK	= 0x90000;
+
+/* should be parameterized but is not, yuck! */
+_ROMBASE	= 0x80000;
+
+/*
+ *	Entry point is not really nececary, since the mkrom(8)
+ *	tool creates a entry point that jumps to $0xc000:0x0000.
+ */
+/* baloney, but ... RGM*/
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	 * First we place the code and read only data (typically const declared).
+	 * This get placed in rom.
+	 */
+	.text _ROMBASE : {
+		_text = .;
+		*(.text);
+		*(.rodata);
+		_etext = .;
+	}
+
+	_pdata = .;
+
+/*
+	.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +  
+					SIZEOF(.rodata)) {
+ */
+	.pdata _PDATABASE : AT ( _etext ) {
+		*(.pdata);
+	}
+
+	_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
+
+	/*
+	 * After the code we place initialized data (typically initialized
+	 * global variables). This gets copied into ram by startup code.
+	 * __data_start and __data_end shows where in ram this should be placed,
+	 * whereas __data_loadstart and __data_loadend shows where in rom to
+	 * copy from.
+	 */
+	.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
+		_data = .;
+		*(.data)
+		*(.sdata)
+		*(.sdata2)
+		*(.got)
+		_edata = .;
+	}
+    
+	_ldata	= LOADADDR(.data);
+	_eldata	= LOADADDR(.data) + SIZEOF(.data);
+ 	
+	/*
+	 * bss does not contain data, it is just a space that should be zero
+	 * initialized on startup. (typically uninitialized global variables)
+	 * crt0.S fills between __bss_start and __bss_end with zeroes.
+	 */
+	.bss ( ADDR(.data) + SIZEOF(.data) ) : {
+		_bss = .;
+		*(.bss)
+		*(.sbss)
+		*(COMMON)
+		_ebss = .;
+		_heap = .;
+	}
+}
+
+/*
+ *	This provides the start and end address for the whole image 
+ */
+_image	= LOADADDR(.text);
+_eimage	= LOADADDR(.data) + SIZEOF(.data);
+
+/* EOF */
diff --git a/src/lib/serial_subr.c b/src/lib/serial_subr.c
new file mode 100644
index 0000000000..d1cbafc2d8
--- /dev/null
+++ b/src/lib/serial_subr.c
@@ -0,0 +1,77 @@
+
+#include <cpu/p5/io.h>
+#include "serial_subr.h"
+
+/* Base Address */
+#define TTYS0 0x3f8
+
+/* Data */
+#define TTYS0_RBR (TTYS0+0x00)
+
+/* Control */
+#define TTYS0_TBR TTYS0_RBR
+#define TTYS0_IER (TTYS0+0x01)
+#define TTYS0_IIR (TTYS0+0x02)
+#define TTYS0_FCR TTYS0_IIR
+#define TTYS0_LCR (TTYS0+0x03)
+#define TTYS0_MCR (TTYS0+0x04)
+#define TTYS0_DLL TTYS0_RBR
+#define TTYS0_DLM TTYS0_IER
+
+/* Status */
+#define TTYS0_LSR (TTYS0+0x05)
+#define TTYS0_MSR (TTYS0+0x06)
+#define TTYS0_SCR (TTYS0+0x07)
+
+void ttys0_tx_char(char data) {
+  while (!(inb(TTYS0_LSR) & 0x20));
+  outb(data, TTYS0_TBR);
+}
+
+void ttys0_tx_string(char *data) {
+
+  while (*data) {
+    if (*data=='\n') ttys0_tx_char('\r');
+    ttys0_tx_char(*data++);
+  }
+}
+
+void ttys0_tx_hex_digit(char data) {
+
+  data &= 0x0f;
+
+  if (data>9) {
+    data += ('a'-10);
+  }
+  else {
+    data += '0';
+  }
+
+  ttys0_tx_char(data);
+}
+
+void ttys0_tx_hex(unsigned int data, int digits) {
+  int ii;
+
+  /* ttys0_tx_string("0x"); */
+
+  for (ii = 0; ii<digits; ii++) {
+    ttys0_tx_hex_digit((char)(data >> ((digits - ii - 1)*4)));
+  }
+}
+
+void ttys0_tx_int(int data) {
+  int ii, i2;
+  int digit[30];
+
+  ii = 0;
+
+  do {
+    digit[ii] = data % 10;
+    data = data/10;
+  } while ((ii++ < 30) && data);
+
+  for (i2=0; i2<ii; i2++) {
+    ttys0_tx_hex_digit((char)digit[ii-i2-1]);
+  }
+}
diff --git a/src/superio/sis/950/setup_serial.inc b/src/superio/sis/950/setup_serial.inc
new file mode 100644
index 0000000000..53d069cce5
--- /dev/null
+++ b/src/superio/sis/950/setup_serial.inc
@@ -0,0 +1,43 @@
+#define OUTIT(val, port) movb val, %al; \
+	outb %al, port
+
+#define OUT2E(val) OUTIT(val, $0x2e)
+#define OUT2F(val) OUTIT(val, $0x2f)
+/* to do: move this to a common include file! */
+#define WRITESIOBYTE(register, value) movw register, %dx ;\
+				movb value, %al ;\
+				outb %al, %dx
+#define WRITESIOWORD(register, value) movw register, %dx ;\
+				movw value, %ax ;\
+				outw %ax, %dx
+
+/* turn on PnP */
+	OUT2E($0x87)
+	OUT2E($1)
+	OUT2E($0x55)
+	OUT2E($0x55)
+
+/* select com1 */
+	OUT2E($7)
+	OUT2F($1)
+/* set the enable in reg. 0x30 */
+	OUT2E($0x30)
+	OUT2F($1)
+/* turn off PnP */
+	OUT2E($2)
+	OUT2F($2)
+/* all done that nonsense -- from here on it's standard pc80 */
+// set up register to set baud rate.
+	WRITESIOBYTE($0x3fb, $0x80)
+// Set 115 kb
+	WRITESIOWORD($0x3f8, $1)
+// Set 9.6 kb
+//	WRITESIOWORD($0x3f8, $12)
+// now set no parity, one stop, 8 bits
+	WRITESIOBYTE($0x3fb, $3)
+// now turn on RTS, DRT
+	WRITESIOBYTE($0x3fc, $3)
+// Enable interrupts
+	WRITESIOBYTE($0x3f9, $0xf)
+// should be done. Dump a char for fun.
+	WRITESIOBYTE($0x3f8, $48)